Hossein Asadi

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 64

Top Topics

Replacement Policy

Reconfigurable Architecture

Top Venues

IEEE Trans. Computers

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Eric Borba, Reza Salkhordeh, Salim Mimouni, Eduardo Tavares, Paulo Maciel, Hossein Asadi, André Brinkmann
A Hierarchical Modeling Approach for Assessing the Reliability and Performability of Burst Buffers. ARCS (2024)
Mostafa Kishani, Zdenek Becvar, Mohammadsaleh Nikooroo, Hossein Asadi
Joint Optimization of Communication and Storage Latencies for Vehicular Edge Computing. IEEE Trans. Intell. Transp. Syst. 25 (6) (2024)
Zeinab Seifoori, Behzad Omidi, Hossein Asadi
PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era. IEEE Trans. Very Large Scale Integr. Syst. 31 (12) (2023)
Mohammadamin Ajdari, Pouria Peykani Sani, Amirhossein Moradi, Masoud Khanalizadeh Imani, Amir Hossein Bazkhanei, Hossein Asadi
Re-architecting I/O Caches for Emerging Fast Storage Devices. ASPLOS (3) (2023)
Mohammadamin Ajdari, Patrick Raaf, Mostafa Kishani, Reza Salkhordeh, Hossein Asadi, André Brinkmann
An Enterprise-Grade Open-Source Data Reduction Architecture for All-Flash Storage Systems. SIGMETRICS (Abstracts) (2022)
Shahriar Ebrahimi, Reza Salkhordeh, Seyed Ali Osia, Ali Taheri, Hamid R. Rabiee, Hossein Asadi
RC-RNN: Reconfigurable Cache Architecture for Storage Systems Using Recurrent Neural Networks. IEEE Trans. Emerg. Top. Comput. 10 (3) (2022)
Mostafa Kishani, Zdenek Becvar, Mohammadsaleh Nikooroo, Hossein Asadi
Reducing Storage and Communication Latencies in Vehicular Edge Cloud. EuCNC (2022)
Elham Cheshmikhani, Hamed Farbeh, Seyed Ghassem Miremadi, Hossein Asadi
TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches. CoRR (2022)
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison. IEEE Trans. Computers 71 (6) (2022)
Mostafa Hadizadeh, Elham Cheshmikhani, Maysam Rahmanpour, Onur Mutlu, Hossein Asadi
CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers. IEEE Trans. Parallel Distributed Syst. 33 (10) (2022)
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches. CoRR (2022)
Mohammadamin Ajdari, Patrick Raaf, Mostafa Kishani, Reza Salkhordeh, Hossein Asadi, André Brinkmann
An Enterprise-Grade Open-Source Data Reduction Architecture for All-Flash Storage Systems. Proc. ACM Meas. Anal. Comput. Syst. 6 (2) (2022)
Mostafa Hadizadeh, Elham Cheshmikhani, Maysam Rahmanpour, Onur Mutlu, Hossein Asadi
CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers. CoRR (2022)
Mojtaba Tarihi, Soheil Azadvar, Arash Tavakkol, Hossein Asadi, Hamid Sarbazi-Azad
Quick Generation of SSD Performance Models Using Machine Learning. IEEE Trans. Emerg. Top. Comput. 10 (4) (2022)
Saba Ahmadian, Reza Salkhordeh, Onur Mutlu, Hossein Asadi
ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms. CoRR (2021)
Mostafa Kishani, Mehdi B. Tahoori, Hossein Asadi
Dependability Analysis of Data Storage Systems in Presence of Soft Errors. CoRR (2021)
Shahriar Ebrahimi, Reza Salkhordeh, Seyed Ali Osia, Ali Taheri, Hamid Reza Rabiee, Hossein Asadi
RC-RNN: Reconfigurable Cache Architecture for Storage Systems Using Recurrent Neural Networks. CoRR (2021)
Mostafa Kishani, Saba Ahmadian, Hossein Asadi
A Modeling Framework for Reliability of Erasure Codes in SSD Arrays. CoRR (2021)
Saba Ahmadian, Reza Salkhordeh, Onur Mutlu, Hossein Asadi
ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms. IEEE Trans. Parallel Distributed Syst. 32 (10) (2021)
Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic
Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing. IEEE Access 9 (2021)
Mostafa Kishani, Zdenek Becvar, Hossein Asadi
PADSA: Priority-Aware Block Data Storage Architecture for Edge Cloud Serving Autonomous Vehicles. VNC (2021)
Saba Ahmadian, Farhad Taheri, Hossein Asadi
Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems. IEEE Trans. Emerg. Top. Comput. 9 (4) (2021)
Mostafa Hadizadeh, Elham Cheshmikhani, Hossein Asadi
STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation. DATE (2020)
Mostafa Kishani, Saba Ahmadian, Hossein Asadi
A Modeling Framework for Reliability of Erasure Codes in SSD Arrays. IEEE Trans. Computers 69 (5) (2020)
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches. IEEE Trans. Reliab. 69 (2) (2020)
Reza Salkhordeh, Onur Mutlu, Hossein Asadi
An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories. CoRR (2019)
Elham Cheshmikhani, Hamed Farbeh, Seyed Ghassem Miremadi, Hossein Asadi
TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches. IEEE Trans. Computers 68 (3) (2019)
Mostafa Kishani, Mehdi Baradaran Tahoori, Hossein Asadi
Dependability Analysis of Data Storage Systems in Presence of Soft Errors. IEEE Trans. Reliab. 68 (1) (2019)
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches. ASP-DAC (2019)
Sajjad Tamimi, Zahra Ebrahimi, Behnam Khaleghi, Hossein Asadi
An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (3) (2019)
Omid Ranjbar, Siavash Bayat Sarmadi, Fatemeh Pooyan, Hossein Asadi
A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs. J. Electron. Test. 35 (2) (2019)
Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi
Estimating and Mitigating Aging Effects in Routing Network of FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 27 (3) (2019)
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation. DATE (2019)
Saba Ahmadian, Farhad Taheri, Hossein Asadi
Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems. CoRR (2019)
Reza Salkhordeh, Mostafa Hadizadeh, Hossein Asadi
An Efficient Hybrid I/O Caching Architecture Using Heterogeneous SSDs. IEEE Trans. Parallel Distributed Syst. 30 (6) (2019)
Saba Ahmadian, Reza Salkhordeh, Hossein Asadi
LBICA: A Load Balancer for I/O Cache Architectures. DATE (2019)
Reza Salkhordeh, Onur Mutlu, Hossein Asadi
An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories. IEEE Trans. Computers 68 (8) (2019)
Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic
A Machine Learning Approach for Power Gating the FPGA Routing Network. FPT (2019)
Saba Ahmadian, Farhad Taheri, Mehrshad Lotfi, Maryam Karimi, Hossein Asadi
Investigating power outage effects on reliability of solid-state drives. DATE (2018)
Saba Ahmadian, Onur Mutlu, Hossein Asadi
ECI-Cache: A High-Endurance and Cost-Efficient I/O Caching Scheme for Virtualized Platforms. CoRR (2018)
Reza Salkhordeh, Shahriar Ebrahimi, Hossein Asadi
ReCA: An Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization. IEEE Trans. Parallel Distributed Syst. 29 (7) (2018)
Reza Salkhordeh, Mostafa Hadizadeh, Hossein Asadi
An Efficient Hybrid I/O Caching Architecture Using Heterogeneous SSDs. CoRR (2018)
Saba Ahmadian, Onur Mutlu, Hossein Asadi
ECI-Cache: A High-Endurance and Cost-Efficient I/O Caching Scheme for Virtualized Platforms. Proc. ACM Meas. Anal. Comput. Syst. 2 (1) (2018)
Reza Salkhordeh, Hossein Asadi
An Operating System Level Data Migration Scheme in Hybrid DRAM-NVM Memory Architecture. CoRR (2018)
Saba Ahmadian, Onur Mutlu, Hossein Asadi
ECI-Cache: A High-Endurance and Cost-Efficient I/O Caching Scheme for Virtualized Platforms. SIGMETRICS (Abstracts) (2018)
Saba Ahmadian, Farhad Taheri, Mehrshad Lotfi, Maryam Karimi, Hossein Asadi
Investigating Power Outage Effects on Reliability of Solid-State Drives. CoRR (2018)
Reza Salkhordeh, Shahriar Ebrahimi, Hossein Asadi
ReCA: an Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization. CoRR (2018)
Behnam Khaleghi, Hossein Asadi
A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2018)
Mostafa Kishani, Reza Eftekhari, Hossein Asadi
Evaluating Impact of Human Errors on the Availability of Data Storage Systems. CoRR (2018)
Mostafa Kishani, Hossein Asadi
Modeling Impact of Human Errors on the Data Unavailability and Data Loss of Storage Systems. CoRR (2018)
Mostafa Kishani, Hossein Asadi
Modeling Impact of Human Errors on the Data Unavailability and Data Loss of Storage Systems. IEEE Trans. Reliab. 67 (3) (2018)
Saba Ahmadian, Reza Salkhordeh, Hossein Asadi
LBICA: A Load Balancer for I/O Cache Architectures. CoRR (2018)
Zeinab Seifoori, Zahra Ebrahimi, Behnam Khaleghi, Hossein Asadi
Chapter Seven - Introduction to Emerging SRAM-Based FPGA Architectures in Dark Silicon Era. Adv. Comput. 110 (2018)
Zahra Ebrahimi, Behnam Khaleghi, Hossein Asadi
PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era. IEEE Trans. Computers 66 (6) (2017)
Zeinab Seifoori, Behnam Khaleghi, Hossein Asadi
A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era. DATE (2017)
Mostafa Kishani, Reza Eftekhari, Hossein Asadi
Evaluating impact of human errors on the availability of data storage systems. DATE (2017)
Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad
Introduction: Special Section on Architecture of Future Many Core Systems. Microprocess. Microsystems 46 (2016)
Hamed Farbeh, Nooshin Sadat Mirzadeh, Nahid Farhady Ghalaty, Seyed Ghassem Miremadi, Mahdi Fazeli, Hossein Asadi
A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 24 (11) (2016)
Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad
Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems. IEEE Trans. Computers 65 (4) (2016)
Mojtaba Ebrahimi, Hossein Asadi, Rajendra Bishnoi, Mehdi Baradaran Tahoori
Layout-Based Modeling and Mitigation of Multiple Event Transients. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (3) (2016)
Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi
Stress-aware routing to mitigate aging effects in SRAM-based FPGAs. FPL (2016)
Reza Salkhordeh, Hossein Asadi
An Operating System level data migration scheme in hybrid DRAM-NVM memory architecture. DATE (2016)
Mojtaba Tarihi, Hossein Asadi, Alireza Haghdoost, Mohammad Arjomand, Hamid Sarbazi-Azad
A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization. IEEE Trans. Computers 65 (6) (2016)
Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi
Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. IEEE Trans. Very Large Scale Integr. Syst. 24 (12) (2016)
Iman Ahmadpour, Behnam Khaleghi, Hossein Asadi
An efficient reconfigurable architecture by characterizing most frequent logic functions. FPL (2015)
Reza Salkhordeh, Hossein Asadi, Shahriar Ebrahimi
Operating system level data tiering using online workload characterization. J. Supercomput. 71 (4) (2015)
Saeideh Alinezhad Chamazcoti, Ziba Delavari, Seyed Ghassem Miremadi, Hossein Asadi
On endurance and performance of erasure codes in SSD-based storage systems. Microelectron. Reliab. 55 (11) (2015)
Mojtaba Tarihi, Hossein Asadi, Hamid Sarbazi-Azad
DiskAccel: Accelerating Disk-Based Experiments by Representative Sampling. SIGMETRICS (2015)
Behnam Khaleghi, Ali Ahari, Hossein Asadi, Siavash Bayat Sarmadi
FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic. IEEE Embed. Syst. Lett. 7 (2) (2015)
Sadegh Yazdanshenas, Hossein Asadi, Behnam Khaleghi
A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Sadegh Yazdanshenas, Hossein Asadi
Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices. IEEE Trans. Circuits Syst. II Express Briefs (10) (2014)
Ali Ahari, Hossein Asadi, Mehdi Baradaran Tahoori
Emerging Non-Volatile Memory technologies for future low power reconfigurable systems. ReCoSoC (2014)
Ali Ahari, Behnam Khaleghi, Zahra Ebrahimi, Hossein Asadi, Mehdi Baradaran Tahoori
Towards dark silicon era in FPGAs using complementary hard logic design. FPL (2014)
Siavash Rezaei, Seyed Ghassem Miremadi, Hossein Asadi, Mahdi Fazeli
Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates. Microelectron. Reliab. 54 (6-7) (2014)
Hossein Asadi, Alireza Haghdoost, Morteza Ramezani, Nima Elyasi, Amirali Baniasadi
CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors. Microelectron. Reliab. 54 (5) (2014)
Ali Ahari, Hossein Asadi, Behnam Khaleghi, Mehdi Baradaran Tahoori
A power-efficient reconfigurable architecture using PCM configuration technology. DATE (2014)
Mojtaba Ebrahimi, Hossein Asadi, Mehdi Baradaran Tahoori
A layout-based approach for multiple event transient analysis. DAC (2013)
Mojtaba Ebrahimi, Seyed Ghassem Miremadi, Hossein Asadi, Mahdi Fazeli
Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems. IEEE Trans. Very Large Scale Integr. Syst. 21 (8) (2013)
Mojtaba Ebrahimi, Liang Chen, Hossein Asadi, Mehdi Baradaran Tahoori
CLASS: Combined logic and architectural soft error sensitivity analysis. ASP-DAC (2013)
Mohammad Hossein Hajkazemi, Amirali Baniasadi, Hossein Asadi
FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications. ASAP (2013)
Amir Mahdi Hosseini Monazzah, Hamed Farbeh, Seyed Ghassem Miremadi, Mahdi Fazeli, Hossein Asadi
FTSPM: A Fault-Tolerant ScratchPad Memory. DSN (2013)
Hossein Asadi, Mehdi Baradaran Tahoori, Mahdi Fazeli, Seyed Ghassem Miremadi
Efficient algorithms to accurately compute derating factors of digital circuits. Microelectron. Reliab. 52 (6) (2012)
Mahdi Fazeli, Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori
Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs). DATE (2011)
Mojtaba Ebrahimi, Seyed Ghassem Miremadi, Hossein Asadi
ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications. DATE (2011)
Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori
A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits. DSD (2010)
Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Seyed Nematollah Ahmadian
A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design. DSN (2010)
Hossein Asadi, Mehdi Baradaran Tahoori
Soft error modeling and remediation techniques in ASIC designs. Microelectron. J. 41 (8) (2010)
Alireza Haghdoost, Hossein Asadi, Amirali Baniasadi
System-Level Vulnerability Estimation for Data Caches. PRDC (2010)
Mehdi Baradaran Tahoori, Hossein Asadi, Brian Mullins, David R. Kaeli
Obtaining FPGA soft error rate in high performance information systems. Microelectron. Reliab. 49 (5) (2009)
Brian Mullins, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli, Kevin Granlund, Rudy Bauer, Scott Romano
Case Study: Soft Error Rate Analysis in Storage Systems. VTS (2007)
Hossein Asadi, Mehdi Baradaran Tahoori, Chandra Tirumurti
Estimating Error Propagation Probabilities with Bounded Variances. DFT (2007)
Hossein Asadi, Mehdi Baradaran Tahoori
Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs. IEEE Trans. Very Large Scale Integr. Syst. 15 (12) (2007)
Vilas Sridharan, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli
Reducing Data Cache Susceptibility to Soft Errors. IEEE Trans. Dependable Secur. Comput. 3 (4) (2006)
Hossein Asadi, Mehdi Baradaran Tahoori
Soft error derating computation in sequential circuits. ICCAD (2006)
Hossein Asadi, Mehdi Baradaran Tahoori
Soft error hardening for logic-level designs. ISCAS (2006)
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli
Vulnerability analysis of L2 cache elements to single event upsets. DATE (2006)
Hossein Asadi, Mehdi Baradaran Tahoori
Soft Error Modeling and Protection for Sequential Elements. DFT (2005)
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli
Balancing Performance and Reliability in the Memory Hierarchy. ISPASS (2005)