Sadegh Yazdanshenas

Publication Activity (10 Years)

Years Active: 2014-2020
Publications (10 Years): 15

Top Topics

Convolutional Neural Network

Hardware Implementation

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Mohamed Eldafrawy, Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz
FPGA Logic Block Architectures for Efficient Deep Learning Inference. ACM Trans. Reconfigurable Technol. Syst. 13 (3) (2020)
Andrew Boutros, Mohamed Eldafrawy, Sadegh Yazdanshenas, Vaughn Betz
Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs. FPGA (2019)
Sadegh Yazdanshenas, Vaughn Betz
COFFE 2: Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures. ACM Trans. Reconfigurable Technol. Syst. 12 (1) (2019)
Sadegh Yazdanshenas, Vaughn Betz
The Costs of Confidentiality in Virtualized FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 27 (10) (2019)
Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz
Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs. ACM Trans. Reconfigurable Technol. Syst. 11 (1) (2018)
Sadegh Yazdanshenas, Vaughn Betz
Improving Confidentiality in Virtualized FPGAs. FPT (2018)
Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz
Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs. FPL (2018)
Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz
You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference. ACM Trans. Reconfigurable Technol. Syst. 11 (3) (2018)
Sadegh Yazdanshenas, Vaughn Betz
Interconnect Solutions for Virtualized Field-Programmable Gate Arrays. IEEE Access 6 (2018)
Sadegh Yazdanshenas, Vaughn Betz
Automatic circuit design and modelling for heterogeneous FPGAs. FPT (2017)
Sadegh Yazdanshenas, Vaughn Betz
Quantifying and mitigating the costs of FPGA virtualization. FPL (2017)
Sadegh Yazdanshenas, Kosuke Tatsumura, Vaughn Betz
Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration. FPGA (2017)
Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi
Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. IEEE Trans. Very Large Scale Integr. Syst. 24 (12) (2016)
Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz
High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs. FPT (2016)
Sadegh Yazdanshenas, Hossein Asadi, Behnam Khaleghi
A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Sadegh Yazdanshenas, Marzieh Ranjbar Pirbasti, Mahdi Fazeli, Ahmad Patooghy
Coding Last Level STT-RAM Cache for High Endurance and Low Power. IEEE Comput. Archit. Lett. 13 (2) (2014)
Sadegh Yazdanshenas, Hossein Asadi
Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices. IEEE Trans. Circuits Syst. II Express Briefs (10) (2014)