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Coding Last Level STT-RAM Cache for High Endurance and Low Power.
Sadegh Yazdanshenas
Marzieh Ranjbar Pirbasti
Mahdi Fazeli
Ahmad Patooghy
Published in:
IEEE Comput. Archit. Lett. (2014)
Keyphrases
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low power
power consumption
low cost
high speed
low power consumption
single chip
vlsi architecture
vlsi circuits
high power
deblocking filter
digital signal processing
image sensor
wireless transmission
power dissipation
logic circuits
real time
mixed signal
coding scheme
low density parity check
delay insensitive
cmos technology
low complexity