Coding Last Level STT-RAM Cache for High Endurance and Low Power.
Sadegh YazdanshenasMarzieh Ranjbar PirbastiMahdi FazeliAhmad PatooghyPublished in: IEEE Comput. Archit. Lett. (2014)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- low power consumption
- single chip
- vlsi architecture
- vlsi circuits
- high power
- deblocking filter
- digital signal processing
- image sensor
- wireless transmission
- power dissipation
- logic circuits
- real time
- mixed signal
- coding scheme
- low density parity check
- delay insensitive
- cmos technology
- low complexity