Siavash Bayat Sarmadi

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 33

Top Topics

Hardware Architecture

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Internet Things J.

ISC Int. J. Inf. Secur.

Publications

Hatameh Mosanaei-Boorani, Siavash Bayat Sarmadi
A Digital Signature Architecture Suitable for V2V Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (2) (2024)
Farhad Taheri, Siavash Bayat Sarmadi, Hamed Rastaghi
PartialHD: Toward Efficient Hyperdimensional Computing by Partial Processing. IEEE Internet Things J. 11 (1) (2024)
Farhad Taheri, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani, Reza Taheri
Fixflow: A Framework to Evaluate Fixed-point Arithmetic in Light-Weight CNN Inference. CoRR (2023)
Farhad Taheri Ardakani, Siavash Bayat Sarmadi
MISC: Multi-Input Secure Two-Party Computation. ISC Int. J. Inf. Secur. 15 (2) (2023)
Farhad Taheri, Siavash Bayat Sarmadi, Alireza Sadeghpour, Seyed Parsa Tayefeh Morsal
Comprehensive Evaluation of RSB and Spectre Vulnerability on Modern Processors. CoRR (2023)
Mohammad Erfan Mazaheri, Siavash Bayat Sarmadi, Farhad Taheri Ardakani
A Study of Timing Side-Channel Attacks and Countermeasures on JavaScript and WebAssembly. ISC Int. J. Inf. Secur. 14 (1) (2022)
Farhad Taheri, Siavash Bayat Sarmadi, Shahriar Ebrahimi
Efficient Hardware Implementations of Legendre Symbol Suitable for MPC Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (3) (2022)
Shahriar Hadayeghparast, Siavash Bayat Sarmadi, Shahriar Ebrahimi
High-Speed Post-Quantum Cryptoprocessor Based on RISC-V Architecture for IoT. IEEE Internet Things J. 9 (17) (2022)
Mohammad Hossein Farzam, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani, Armin Alivand
Fast Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Customized Pipelined Montgomery Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (3) (2022)
Farhad Taheri, Siavash Bayat Sarmadi, Shahriar Hadayeghparast
RISC-HD: Lightweight RISC-V Processor for Efficient Hyperdimensional Computing Inference. IEEE Internet Things J. 9 (23) (2022)
Mohammad Hossein Farzam, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani, Armin Alivand
Hardware Architecture for Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Fast Montgomery Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (5) (2021)
Shahriar Ebrahimi, Siavash Bayat Sarmadi
Lightweight Fuzzy Extractor Based on LPN for Device and Biometric Authentication in IoT. IEEE Internet Things J. 8 (13) (2021)
Mohsen Salehi, Siavash Bayat Sarmadi
PLCDefender: Improving Remote Attestation Techniques for PLCs Using Physical Model. IEEE Internet Things J. 8 (9) (2021)
Nastaran Shekofte, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani
A Trusted Design Platform for Trojan Detection in FPGA Bitstreams Using Partial Reconfiguration. ISC Int. J. Inf. Secur. 13 (1) (2021)
Shahriar Ebrahimi, Siavash Bayat Sarmadi
Lightweight and Fault-Resilient Implementations of Binary Ring-LWE for IoT Devices. IEEE Internet Things J. 7 (8) (2020)
Mohammad Hossein Farzam, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani
Implementation of Supersingular Isogeny-Based Diffie-Hellman and Key Encapsulation Using an Efficient Scheduling. IEEE Trans. Circuits Syst. (12) (2020)
Mohammad Erfan Mazaheri, Farhad Taheri, Siavash Bayat Sarmadi
Lurking Eyes: A Method to Detect Side-Channel Attacks on JavaScript and WebAssembly. ISCISC (2020)
Taha Shahroodi, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani
Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain Over $GF(2^m)$. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2019)
Raziyeh Salarifard, Siavash Bayat Sarmadi
An Efficient Low-Latency Point-Multiplication Over Curve25519. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2019)
Mohammad Sadegh Sadeghi, Siavash Bayat Sarmadi, Shaahin Hessabi
Toward On-chip Network Security Using Runtime Isolation Mapping. ACM Trans. Archit. Code Optim. 16 (3) (2019)
Omid Ranjbar, Siavash Bayat Sarmadi, Fatemeh Pooyan, Hossein Asadi
A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs. J. Electron. Test. 35 (2) (2019)
Shahriar Ebrahimi, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani
Post-Quantum Cryptoprocessors Optimized for Edge and Resource-Constrained Devices in IoT. IEEE Internet Things J. 6 (3) (2019)
Mehran Mozaffari Kermani, Siavash Bayat Sarmadi, A.-Bon E. Ackie, Reza Azarderakhsh
High-Performance Fault Diagnosis Schemes for Efficient Hash Algorithm BLAKE. LASCAS (2019)
Raziyeh Salarifard, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani
A Low-Latency and Low-Complexity Point-Multiplication in ECC. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2018)
Mehran Mozaffari Kermani, Reza Azarderakhsh, Siavash Bayat Sarmadi
Reliable hardware architectures for efficient secure hash functions ECHO and fugue. CF (2018)
Mehran Mozaffari Kermani, Reza Azarderakhsh, Siavash Bayat Sarmadi
Lightweight Hardware Architectures for Efficient Secure Hash Functions ECHO and Fugue. CoRR (2018)
Mohammad Hossein Yalame, Mohammad Hossein Farzam, Siavash Bayat Sarmadi
Secure Two-Party Computation Using an Efficient Garbled Circuit by Reducing Data Transfer. ATIS (2017)
Ahmad Boorghany, Siavash Bayat Sarmadi, Rasool Jalili
Efficient Lattice-based Authenticated Encryption: A Practice-Oriented Provable Security Approach. IACR Cryptol. ePrint Arch. 2016 (2016)
Raziyeh Salarifard, Siavash Bayat Sarmadi, Mohammad Farmani
) in Dual and Triangular Bases. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2016)
Reza Azarderakhsh, Mehran Mozaffari Kermani, Siavash Bayat Sarmadi, Chiou-Yng Lee
Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Ahmad Boorghany, Siavash Bayat Sarmadi, Rasool Jalili
On Constrained Implementation of Lattice-Based Cryptographic Primitives and Schemes on Smart Cards. ACM Trans. Embed. Comput. Syst. 14 (3) (2015)
Siavash Bayat Sarmadi, Mohammad Farmani
) Based on Trinomials. IEEE Trans. Circuits Syst. II Express Briefs (4) (2015)
Behnam Khaleghi, Ali Ahari, Hossein Asadi, Siavash Bayat Sarmadi
FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic. IEEE Embed. Syst. Lett. 7 (2) (2015)
Siavash Bayat Sarmadi, Mehran Mozaffari Kermani, Arash Reyhani-Masoleh
Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (7) (2014)
Ahmad Boorghany, Siavash Bayat Sarmadi, Rasool Jalili
On Constrained Implementation of Lattice-based Cryptographic Primitives and Schemes on Smart Cards. IACR Cryptol. ePrint Arch. 2014 (2014)
Ahmad Boorghany, Siavash Bayat Sarmadi, Pamian Yousefi, Pouneh Gorji, Rasool Jalili
Random data and key generation evaluation of some commercial tokens and smart cards. ISCISC (2014)
Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee, Siavash Bayat Sarmadi
). IEEE Trans. Very Large Scale Integr. Syst. 22 (5) (2014)
Mehran Mozaffari Kermani, Kai Tian, Reza Azarderakhsh, Siavash Bayat Sarmadi
Fault-Resilient Lightweight Cryptographic Block Ciphers for Secure Embedded Systems. IEEE Embed. Syst. Lett. 6 (4) (2014)
Siavash Bayat Sarmadi, Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee
Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures. IEEE Trans. Circuits Syst. II Express Briefs (2) (2014)
Siavash Bayat Sarmadi, M. Anwar Hasan
Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures. IEEE Trans. Computers 58 (11) (2009)
Siavash Bayat Sarmadi, M. Anwar Hasan
On Concurrent Detection of Errors in Polynomial Basis Multiplication. IEEE Trans. Very Large Scale Integr. Syst. 15 (4) (2007)
Siavash Bayat Sarmadi, M. Anwar Hasan
Run-Time Error Detection in Polynomial Basis Multiplication Using Linear Codes. ASAP (2007)
Siavash Bayat Sarmadi, M. Anwar Hasan
Detecting errors in a polynomial basis multiplier using multiple parity bits for both inputs. ICCD (2007)
Siavash Bayat Sarmadi, M. Anwar Hasan
Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme. DFT (2005)
Ali Reza Ejlali, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi
A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation. DSN (2003)
Siavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza Ejlali
Fast Prototyping with Co-operation of Simulation and Emulation. FPL (2002)
Seyed Ghassem Miremadi, Siavash Bayat Sarmadi, Ghazanfar Asadi
Speedup analysis in simulation-emulation co-operation. FPT (2002)