Hamid R. Zarandi

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 32

Top Topics

Fault Tree Analysis

Design Space Exploration

Failure Detection

Embedded Systems

Top Venues

Microprocess. Microsystems

Microelectron. Reliab.

J. Circuits Syst. Comput.

Publications

Amir M. Hajisadeghi, Mahmoud Momtazpour, Hamid R. Zarandi
Approx-IMC: A general-purpose approximate digital in-memory computing framework based on STT-MRAM. Future Gener. Comput. Syst. 160 (2024)
Alireza Borhani, Hamid R. Zarandi
ThingsDND: IoT Device Failure Detection and Diagnosis for Multi-User Smart Homes. EDCC (2022)
Salar Hashemi, Amir M. Hajisadeghi, Hamid R. Zarandi
EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis. DSD (2022)
Amir M. Hajisadeghi, Hamid R. Zarandi
CLEAR: A Cross-Layer Soft Error Rate Reduction Method Based on Mitigating DETs in Nanoscale Combinational Logics. Microprocess. Microsystems 85 (2021)
Javad Talafy, Farzaneh Zokaee, Hamid R. Zarandi, Nader Bagherzadeh
A High Performance, Multi-Bit Output Logic-in-Memory Adder. IEEE Trans. Emerg. Top. Comput. 9 (4) (2021)
Saeed Seyedfaraji, Amir M. Hajisadeghi, Javad Talafy, Hamid R. Zarandi
DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories. Microprocess. Microsystems 73 (2020)
Alireza Tajary, Hamid R. Zarandi, Nader Bagherzadeh
IRHT: An SDC detection and recovery architecture based on value locality of instruction binary codes. Microprocess. Microsystems 77 (2020)
Athena Abdi, Hamid R. Zarandi
A meta heuristic-based task scheduling and mapping method to optimize main design challenges of heterogeneous multiprocessor embedded systems. Microelectron. J. 87 (2019)
Athena Abdi, Alain Girault, Hamid R. Zarandi
ERPOT: A Quad-Criteria Scheduling Heuristic to Optimize Execution Time, Reliability, Power Consumption and Temperature in Multicores. IEEE Trans. Parallel Distributed Syst. 30 (10) (2019)
Athena Abdi, Masoomeh Karami, Hamid R. Zarandi
Lifetime Reliability Enhancement in Multiprocessor Systems Through a Fine-Grained System-Level Approach. J. Circuits Syst. Comput. 28 (11) (2019)
Salar Hashemi, Amir M. Hajisadeghi, Hamid R. Zarandi, Saadat Pour-Mozafari
A Fast and Efficient Fault Tree Analysis Using Approximate Computing. EDCC (2019)
Hossein Bardareh, Amir M. Hajisadeghi, Hamid R. Zarandi
A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays. IOLTS (2018)
Masoomeh Karami, Athena Abdi, Hamid R. Zarandi
A cross-layer aging-aware task scheduling approach for multiprocessor embedded systems. Microelectron. Reliab. 85 (2018)
Amir M. Hajisadeghi, Hossein Bardareh, Hamid R. Zarandi
MOMENT: A Cross-Layer Method to Mitigate Multiple Event Transients in Combinational Circuits. DSD (2018)
Farzaneh Zokaee, Hamid R. Zarandi, Lei Jiang
AligneR: A Process-in-Memory Architecture for Short Read Alignment in ReRAMs. IEEE Comput. Archit. Lett. 17 (2) (2018)
Athena Abdi, Hamid R. Zarandi
HYSTERY: a hybrid scheduling and mapping approach to optimize temperature, energy consumption and lifetime reliability of heterogeneous multiprocessor systems. J. Supercomput. 74 (5) (2018)
Saaed S. Faraji, Javad Talafy, Amir M. Hajisadeghi, Hamid R. Zarandi
DUSTER: DUal Source Write TERmination Method for STT-RAM Memories. DSD (2018)
Mohammadreza Nakhkash, Hossein Bardareh, Farzaneh Zokaee, Hamid R. Zarandi
Designing a differential 3R-2bit RRAM cell for enhancing read margin in cross-point RRAM arrays. NORCAS (2017)
Fatemeh Ehsani-Besheli, Hamid R. Zarandi
Context-Aware Anomaly Detection in Embedded Systems. DepCoS-RELCOMEX (2017)
Javad Talafy, Hamid R. Zarandi
Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solution. IOLTS (2017)
Shahab Shoar, Hamid R. Zarandi, Farnad Nasirzadeh, Elham Cheshmikhani
Fast Fault Tree Analysis for Hybrid Uncertainties Using Stochastic Logic Implemented on Field-Programmable Gate Arrays: An Application in Quantitative Assessment and mitigation of Welding Defects Risk. Qual. Reliab. Eng. Int. 33 (7) (2017)
Roghayeh Mojarad, Hossain Kordestani, Hamid R. Zarandi
A Cluster-Based Method to Detect and Correct Anomalies in Sensor Data of Embedded Systems. PDP (2016)
Elham Kashefi, Hamid R. Zarandi, Ann Gordon-Ross
Postponing wearout failures in chip multiprocessors using thermal management and thread migration. ReCoSoC (2016)
Alireza Tajary, Hamid R. Zarandi
An Efficient Soft Error Detection in Multicore Processors Running Server Applications. PDP (2016)
Alireza Tajary, Hamid R. Zarandi
Using instruction result locality and re-execution to mitigate silent data corruptions. Microelectron. Reliab. 62 (2016)
Navid Khoshavi, Mohammad Maghsoudloo, Hamid R. Zarandi
Leveraging the Potential of Control-Flow Error Resilient Techniques in Multithreaded Programs. CoRR (2016)
Maryam Ghane, Hamid R. Zarandi
Gate Merging: An NBTI Mitigation Method to Eliminate Critical Internal Nodes in Digital Circuits. PDP (2016)
Saleh Fakhrali, Hamid R. Zarandi
Double Stairs: A Fault-Tolerant Routing Algorithm for Networks-on-Chip. J. Circuits Syst. Comput. 25 (6) (2016)
Kamran Nasiri, Hamid R. Zarandi
MWPF: A Deadlock Avoidance Fully Adaptive Routing Algorithm in Networks-on-Chip. PDP (2016)
Elham Cheshmikhani, Hamid R. Zarandi
Accelerating Dynamic Fault Tree Analysis Based on Stochastic Logic Utilizing GPGPUs. PDP (2016)
Elham Cheshmikhani, Hamid R. Zarandi
Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates. Microelectron. Reliab. 55 (11) (2015)
Mohammad Maghsoudloo, Hamid R. Zarandi
Design space exploration of non-uniform cache access for soft-error vulnerability mitigation. Microelectron. Reliab. 55 (11) (2015)
Mohammad Maghsoudloo, Hamid R. Zarandi
Reliability improvement in private non-uniform cache architecture using two enhanced structures for coherence protocols and replacement policies. Microprocess. Microsystems 38 (6) (2014)
Mohammad H. Mottaghi, Hamid R. Zarandi
DFTS: A dynamic fault-tolerant scheduling for real-time tasks in multicore processors. Microprocess. Microsystems 38 (1) (2014)
Saleh Fakhrali, Hamid R. Zarandi
Fxy: a Hierarchical Routing Algorithm to Balance Performance and Fault Tolerance in Networks-on-Chip. J. Circuits Syst. Comput. 23 (10) (2014)
Mohammad Maghsoudloo, Hamid R. Zarandi
Cache vulnerability mitigation using an adaptive cache coherence protocol. J. Supercomput. 68 (3) (2014)
Hamid Sarbazi-Azad, Hamid R. Zarandi, Mahdi Fazeli
A parallel clustering algorithm on the star graph and its performance. Math. Comput. Model. 58 (3-4) (2013)
Hananeh Aliee, Hamid R. Zarandi
A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on Field-Programmable Gate Arrays. IEEE Trans. Reliab. 62 (1) (2013)
Fatemeh Khalili, Hamid R. Zarandi
A fault-tolerant core mapping technique in networks-on-chip. IET Comput. Digit. Tech. 7 (6) (2013)
Fatemeh Khalili, Hamid R. Zarandi
A Reliability-Aware Multi-application Mapping Technique in Networks-on-Chip. PDP (2013)
Fatemeh Khalili, Hamid R. Zarandi
A Fault-Tolerant Low-Energy Multi-Application Mapping onto NoC-based Multiprocessors. CSE (2012)
Mohammad Maghsoudloo, Hamid R. Zarandi
Dirty data vulnerability mitigation by means of sharing management in cache coherence protocols. DFT (2012)
Mahroo Zandrahimi, Hamid R. Zarandi, Mohammad H. Mottaghi
Two effective methods to detect anomalies in embedded systems. Microelectron. J. 43 (1) (2012)
Fatemeh Khalili, Hamid R. Zarandi
A fault-aware low-energy spare core allocation in networks-on-chip. NORCHIP (2012)
Hamed Abbasitabar, Hamid R. Zarandi, Ronak Salamat
Susceptibility Analysis of LEON3 Embedded Processor against Multiple Event Transients and Upsets. CSE (2012)
Mohammad Maghsoudloo, Hamid R. Zarandi, Navid Khoshavi
An efficient adaptive software-implemented technique to detect control-flow errors in multi-core architectures. Microelectron. Reliab. 52 (11) (2012)
Ronak Salamat, Hamid R. Zarandi
Fault-tolerance assessment and enhancement in SoCWire interface: A system-on-chip wire. IOLTS (2011)
Hananeh Aliee, Hamid R. Zarandi
A Fault-Tolerant, Dynamically Scheduled Pipeline Structure for Chip Multiprocessors. SAFECOMP (2011)
Hananeh Aliee, Hamid R. Zarandi
An efficient, dynamically adaptive method to tolerate transient faults in multi-core systems. EWDC (2011)
Pooria M. Yaghini, Ashkan Eghbal, Hossein Pedram, Hamid R. Zarandi
Investigation of transient fault effects in synchronous and asynchronous Network on Chip router. J. Syst. Archit. 57 (1) (2011)
Hananeh Aliee, Hamid R. Zarandi, Alireza Tajary
CPU-aware, process-level redundancy to tolerate faults in multi-core. HPCS (2011)
Somayeh Bahramnejad, Hamid R. Zarandi
Mitigation of soft errors in SRAM-based FPGAs using CAD tools. Comput. Electr. Eng. 37 (6) (2011)
Mostafa Kishani, Hamid R. Zarandi, Hossein Pedram, Alireza Tajary, Mohsen Raji, Behnam Ghavami
HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors. Des. Autom. Embed. Syst. 15 (3-4) (2011)
Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes. Microelectron. J. 42 (1) (2011)
Navid Khoshavi, Hamid R. Zarandi, Mohammad Maghsoudloo
Control-flow error recovery using commodity multi-core architecture features. IOLTS (2011)
Somayeh Bahramnejad, Hamid R. Zarandi
An adaptive method to tolerate soft errors in SRAM-based FPGAs. Sci. Iran. 18 (6) (2011)
Navid Khoshavi, Hamid R. Zarandi, Mohammad Maghsoudloo
Control-flow error detection using combining basic and program-level checking in commodity multi-core architectures. SIES (2011)
Mohammad Maghsoudloo, Hamid R. Zarandi, Saadat Pour-Mozafari, Navid Khoshavi
Soft Error Detection Technique in Multi-threaded Architectures Using Control-Flow Monitoring. DSD (2011)
Mohammad Maghsoudloo, Hamid R. Zarandi, Navid Khoshavi
Low-Cost Software-Implemented Error Detection Technique. ISED (2011)
Mahroo Zandrahimi, Alireza Zarei, Hamid R. Zarandi
A Probabilistic Method to Detect Anomalies in Embedded Systems. DFT (2010)
Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs. ASP-DAC (2010)
Alireza Rohani, Hamid R. Zarandi
Two effective methods to mitigate soft error effects in SRAM-based FPGAs. Microelectron. Reliab. 50 (8) (2010)
Pooria M. Yaghini, Ashkan Eghbal, Hossein Pedram, Hamid R. Zarandi
Investigation of Transient Fault Effects in an Asynchronous NoC Router. PDP (2010)
Somayeh Bahramnejad, Hamid R. Zarandi
An Adaptive Redundancy Oriented Method to Tolerate Soft Errors in SRAM-Based FPGAs Using Unused Resources. ARES (2010)
Mohsen Raji, Behnam Ghavami, Hossein Pedram, Hamid R. Zarandi
Process variation-aware performance analysis of asynchronous circuits. Microelectron. J. 41 (2-3) (2010)
Mohsen Raji, Alireza Tajary, Behnam Ghavami, Hossein Pedram, Hamid R. Zarandi
Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations. PATMOS (2010)
Pedram Rajabzadeh, Hamid Sarbazi-Azad, Hamid R. Zarandi, Ebrahim Khodaie, Hashem Hashemi Najaf-abadi, Mohamed Ould-Khaoua
Performance modeling of n-dimensional mesh networks. Perform. Evaluation 67 (12) (2010)
Iman Faraji, Moslem Didehban, Hamid R. Zarandi
Analysis of Transient Faults on a MIPS-Based Dual-Core Processor. ARES (2010)
Hamid R. Zarandi, Mohammad Maghsoudloo, Navid Khoshavi
Two Efficient Software Techniques to Detect and Correct Control-Flow Errors. PRDC (2010)
Ashkan Eghbal, Pooria M. Yaghini, Hossein Pedram, Hamid R. Zarandi
Fault injection-based evaluation of a synchronous NoC router. IOLTS (2009)
Alireza Rohani, Hamid R. Zarandi
An Analysis of Fault Effects and Propagations in AVR Microcontroller ATmega103(L). ARES (2009)
Seyyed Amir Asghari, Hamid R. Zarandi, Hossein Pedram, Morteza Ansarinia, Mohammad Khademi
A Fault Injection Attitude based on Background Debug Mode in Embedded Systems. CDES (2009)
Mohsen Raji, Behnam Ghavami, Hamid R. Zarandi, Hossein Pedram
Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation. PATMOS (2009)
Ashkan Eghbal, Hamid R. Zarandi, Pooria M. Yaghini
Fault tolerance assessment of PIC microcontroller based on fault injection. LATW (2009)
Alireza Rohani, Hamid R. Zarandi
A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs. ReConFig (2009)
Behnam Ghavami, Hamid R. Zarandi, Arezoo Salarpour, Hossein Pedram
Diagnosis of faults in template-based asynchronous circuits. SoC (2009)
Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. ISCAS (2007)
Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. ISCAS (2007)
Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan
Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. DFT (2007)
Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. IPDPS (2007)
Hamid R. Zarandi, Seyed Ghassem Miremadi
Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs. Microelectron. Reliab. 47 (2-3) (2007)
Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan
Multiple Upsets Tolerance in SRAM Memory. ISCAS (2007)
Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. ISQED (2007)
Hamid R. Zarandi, Seyed Ghassem Miremadi
A SEU-protected cache memory-based on variable associativity of sets. Reliab. Eng. Syst. Saf. 92 (11) (2007)
Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. ISCAS (2007)
Hamid R. Zarandi, Seyed Ghassem Miremadi
A fault-tolerant cache architecture based on binary set partitioning. Microelectron. Reliab. 46 (1) (2006)
Hamid R. Zarandi, Seyed Ghassem Miremadi
Hierarchical Set-Associate Cache for High-Performance and Low-Energy Architecture. J. Circuits Syst. Comput. 15 (6) (2006)
Hamid R. Zarandi, Hamid Sarbazi-Azad
Hierarchical Binary Set Partitioning in Cache Memories. J. Supercomput. 31 (2) (2005)
Hamid R. Zarandi, Seyed Ghassem Miremadi
Hierarchical Multiple Associative Mapping in Cache Memories. ECBS (2005)
Hamid R. Zarandi, Seyed Ghassem Miremadi
Soft Error Mitigation in Cache Memories of Embedded Systems by Means of a Protected Scheme. LADC (2005)
Hamid R. Zarandi, Seyed Ghassem Miremadi, Shaahin Hessabi, Ali Reza Ejlali
A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models. ESA/VLSI (2004)
Hamid R. Zarandi, Seyed Ghassem Miremadi, Hamid Sarbazi-Azad
Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm. IOLTS (2004)
Hamid R. Zarandi, Seyed Ghassem Miremadi
A Highly Fault Detectable Cache Architecture for Dependable Computing. SAFECOMP (2004)
Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali
Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs. PRDC (2004)
Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Alireza Ejlali
Fault injection into SRAM-based FPGAs for the analysis of SEU effects. FPT (2003)
Ali Reza Ejlali, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi
A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation. DSN (2003)
Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali
Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems. ISPDC (2003)
Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. DFT (2003)