CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs.
Hamid R. ZarandiSeyed Ghassem MiremadiDhiraj K. PradhanJimson MathewPublished in: ISCAS (2007)
Keyphrases
- power reduction
- high speed
- power consumption
- low power
- hardware implementation
- power saving
- computer aided
- low cost
- field programmable gate array
- computer aided design
- verilog hdl
- analog vlsi
- real time image processing
- computer graphics
- design process
- signal processing
- object oriented
- reduction method
- single chip
- image processing
- neural network
- data sets
- real time