Amir M. Hajisadeghi

Publication Activity (10 Years)

Years Active: 2018-2024
Publications (10 Years): 9

Top Topics

Architectural Design

Compute Intensive

Heterogeneous Computing

Convolutional Neural Networks

Top Venues

Microprocess. Microsystems

Publications

Amir M. Hajisadeghi, Mahmoud Momtazpour, Hamid R. Zarandi
Approx-IMC: A general-purpose approximate digital in-memory computing framework based on STT-MRAM. Future Gener. Comput. Syst. 160 (2024)
Ali Sedaghatgoo, Amir M. Hajisadeghi, Mahmoud Momtazpour, Nader Bagherzadeh
ARMAN: A Reconfigurable Monolithic 3D Accelerator Architecture for Convolutional Neural Networks. CoRR (2024)
Salar Hashemi, Amir M. Hajisadeghi, Hamid R. Zarandi
EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis. DSD (2022)
Amir M. Hajisadeghi, Hamid R. Zarandi
CLEAR: A Cross-Layer Soft Error Rate Reduction Method Based on Mitigating DETs in Nanoscale Combinational Logics. Microprocess. Microsystems 85 (2021)
Saeed Seyedfaraji, Amir M. Hajisadeghi, Javad Talafy, Hamid R. Zarandi
DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories. Microprocess. Microsystems 73 (2020)
Salar Hashemi, Amir M. Hajisadeghi, Hamid R. Zarandi, Saadat Pour-Mozafari
A Fast and Efficient Fault Tree Analysis Using Approximate Computing. EDCC (2019)
Hossein Bardareh, Amir M. Hajisadeghi, Hamid R. Zarandi
A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays. IOLTS (2018)
Amir M. Hajisadeghi, Hossein Bardareh, Hamid R. Zarandi
MOMENT: A Cross-Layer Method to Mitigate Multiple Event Transients in Combinational Circuits. DSD (2018)
Saaed S. Faraji, Javad Talafy, Amir M. Hajisadeghi, Hamid R. Zarandi
DUSTER: DUal Source Write TERmination Method for STT-RAM Memories. DSD (2018)