Morteza Saheb Zamani

ORCID

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 16

Top Venues

CoRR

Quantum Inf. Process.

ACM J. Emerg. Technol. Comput. Syst.

Microprocess. Microsystems

Publications

Vahid Amini, Mahmoud Momtazpour, Morteza Saheb Zamani
An energy-efficient and accuracy-aware edge computing framework for heart arrhythmia detection: A joint model selection and task offloading approach. J. Supercomput. 79 (8) (2023)
Ali Suvizi, Azim Farghadan, Morteza Saheb Zamani
A parallel computing architecture based on cellular automata for hydraulic analysis of water distribution networks. J. Parallel Distributed Comput. 178 (2023)
Eesa Nikahd, Morteza Saheb Zamani, Mehdi Sedighi
Low-overhead code concatenation approaches for universal quantum computation. Quantum Inf. Process. 22 (1) (2023)
Mohammad Hadi Mottaghi, Mehdi Sedighi, Morteza Saheb Zamani
FIFA: A Fully Invertible FPGA Architecture to Reduce BTI-Induced Aging Effects. IEEE Trans. Computers 71 (9) (2022)
Reza Fani, Morteza Saheb Zamani
Runtime hardware Trojan detection by reconfigurable monitoring circuits. J. Supercomput. 78 (10) (2022)
Sahar Darafsh, Saeed Shiry Ghidary, Morteza Saheb Zamani
Real-Time Activity Recognition and Intention Recognition Using a Vision-based Embedded System. CoRR (2021)
Mohammad H. Mottaghi, Mehdi Sedighi, Morteza Saheb Zamani
Aging Mitigation in FPGAs Considering Delay, Power, and Temperature. IEEE Trans. Reliab. 69 (2) (2020)
Ghobad Zarrinchian, Morteza Saheb Zamani
Combinational Counters: A Low Overhead Approach to Address DPA Attacks. J. Circuits Syst. Comput. 29 (6) (2020)
Mona Arabzadeh, Mehdi Sedighi, Morteza Saheb Zamani, Sayed-Amir Marashi
A system architecture for parallel analysis of flux-balanced metabolic pathways. Comput. Biol. Chem. 88 (2020)
Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Sayed-Amir Marashi
A graph-based approach to analyze flux-balanced pathways in metabolic networks. Biosyst. 165 (2018)
Maryam Eslamy, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi
Geometry-Based Optimization of One-Way Quantum Computation Measurement Patterns. CoRR (2017)
Ghobad Zarrinchian, Morteza Saheb Zamani
Latch-Based Structure: A High Resolution and Self-Reference Technique for Hardware Trojan Detection. IEEE Trans. Computers 66 (1) (2017)
Mahboobeh Houshmand, Mehdi Sedighi, Morteza Saheb Zamani, Kourosh Marjoei
Quantum Circuit Synthesis Targeting to Improve One-Way Quantum Computation Pattern Cost Metrics. ACM J. Emerg. Technol. Comput. Syst. 13 (4) (2017)
Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi
One-Way Quantum Computer Simulation. CoRR (2016)
Mehrshad Khosraviani, Morteza Saheb Zamani, Gholamreza Bidkhori
FogLight: an efficient matrix-based approach to construct metabolic pathways by search space reduction. Bioinform. 32 (3) (2016)
Mona Arabzadeh, Mahboobeh Houshmand, Mehdi Sedighi, Morteza Saheb Zamani
Quantum-Logic Synthesis of Hermitian Gates. ACM J. Emerg. Technol. Comput. Syst. 12 (4) (2016)
Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Monireh Houshmand
GA-based approach to find the stabilizers of a given sub-space. Genet. Program. Evolvable Mach. 16 (1) (2015)
Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi
One-way quantum computer simulation. Microprocess. Microsystems 39 (3) (2015)
Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani
A Trust-Driven Placement Approach: A New Perspective on Design for Hardware Trust. J. Circuits Syst. Comput. 24 (8) (2015)
Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani
Improving hardware Trojan detection by retiming. Microprocess. Microsystems 39 (3) (2015)
Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi
Quantum circuit physical design methodology with emphasis on physical synthesis. Quantum Inf. Process. 13 (2) (2014)
Arash Nejat, Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani
A study on the efficiency of hardware Trojan detection based on path-delay fingerprinting. Microprocess. Microsystems 38 (3) (2014)
Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh
Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates. CoRR (2014)
Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh
Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates. ACM J. Emerg. Technol. Comput. Syst. 11 (3) (2014)
Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Mohammad Hossein Samavatian
Automatic translation of quantum circuits to optimized one-way quantum computation patterns. Quantum Inf. Process. 13 (11) (2014)
Seyyed Ahmad Razavi, Morteza Saheb Zamani
Improving bitstream compression by modifying FPGA architecture. FPGA (2013)
Maryam Yazdani, Morteza Saheb Zamani, Mehdi Sedighi
A Quantum Physical Design Flow Using ILP and Graph Drawing. CoRR (2013)
Maryam Yazdani, Morteza Saheb Zamani, Mehdi Sedighi
A quantum physical design flow using ILP and graph drawing. Quantum Inf. Process. 12 (10) (2013)
Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi
Depth-optimized reversible circuit synthesis. Quantum Inf. Process. 12 (4) (2013)
Somayeh Kashi, Morteza Saheb Zamani
Hardware Acceleration of STON Algorithm for Comparing 3-D Structure of Proteins. DSD (2012)
Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi
OWQS: One-Way Quantum Computation Simulator. DSD (2012)
Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani
Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only). FPGA (2012)
Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi
Depth-Optimized Reversible Circuit Synthesis. CoRR (2012)
Mehdi Saeedi, Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi
Block-based quantum-logic synthesis. Quantum Inf. Comput. 11 (3&4) (2011)
Ali Jahanian, Morteza Saheb Zamani, Hamid Safizadeh
Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology. Integr. 44 (2) (2011)
Seyyed Hasan Moallempour, Seyyed Ahmad Razavi, Morteza Saheb Zamani
TSV reduction in homogeneous 3D FPGAs by logic resource and input pad replication. 3DIC (2011)
Behzad Salami, Morteza Saheb Zamani, Ali Jahanian
VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs. DSD (2011)
Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes. Microelectron. J. 42 (1) (2011)
Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani
Evaluation of FPGA routing architectures under process variation. ACM Great Lakes Symposium on VLSI (2011)
Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi
Auxiliary qubit selection: a physical synthesis technique for quantum circuits. Quantum Inf. Process. 10 (2) (2011)
Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
A Library-Based Synthesis Methodology for Reversible Logic. CoRR (2010)
Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, Zahra Sasanian
Reversible Circuit Synthesis Using a Cycle-Based Approach. CoRR (2010)
Mona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani
Rule-Based Optimization of Reversible Circuits. CoRR (2010)
Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs. ASP-DAC (2010)
Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, Zahra Sasanian
Reversible circuit synthesis using a cycle-based approach. ACM J. Emerg. Technol. Comput. Syst. 6 (4) (2010)
Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani
Quantum physical synthesis: Improving physical design by netlist modifications. Microelectron. J. 41 (4) (2010)
Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
A library-based synthesis methodology for reversible logic. Microelectron. J. 41 (4) (2010)
Mehdi Saeedi, Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi
Block-based quantum-logic synthesis. CoRR (2010)
Mona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani
Rule-based optimization of reversible circuits. ASP-DAC (2010)
Ali Jahanian, Morteza Saheb Zamani
Early Buffer Planning with Congestion Control Using Buffer Requirement Map. J. Circuits Syst. Comput. 19 (5) (2010)
Hassan Ebrahimi, Morteza Saheb Zamani, Seyyed Ahmad Razavi
A Switch Box Architecture to Mitigate Bridging and Short Faults in SRAM-Based FPGAs. DFT (2010)
Delasa Aghamirzaie, Seyyed Ahmad Razavi, Morteza Saheb Zamani, Mahdi Nabiyouni
Reduction of process variation effect on FPGAs using multiple configurations. VLSI-SoC (2010)
Seyyed Ahmad Razavi, Morteza Saheb Zamani, Kia Bazargan
A tileable switch module architecture for homogeneous 3D FPGAs. 3DIC (2009)
Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
A cycle-based synthesis algorithm for reversible logic. ASP-DAC (2009)
Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi
Improving Latency of Quantum Circuits by Gate Exchanging. DSD (2009)
Ali Jahanian, Morteza Saheb Zamani
Improved performance and yield with chip master planning design methodology. ACM Great Lakes Symposium on VLSI (2009)
Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian, Morteza Saheb Zamani
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network. DATE (2009)
Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami
Design space exploration for a coarse grain accelerator. ASP-DAC (2008)
Ali Jahanian, Morteza Saheb Zamani
Performance and Timing Yield Enhancement using Highway-on-Chip Planning. DSD (2008)
Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
Synthesis of reversible circuits using a moving forward strategy. IEICE Electron. Express 5 (17) (2008)
Arash Mehdizadeh, Morteza Saheb Zamani
A Novel Crosstalk Estimator after Placement. CSICC (2008)
Arash Mehdizadeh, Morteza Saheb Zamani
Proposing an efficient method to estimate and reduce crosstalk after placement in VLSI circuits. AICCSA (2008)
Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi
Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm. DSD (2008)
Ali Jahanian, Morteza Saheb Zamani
Using metro-on-chip in physical design flow for congestion and routability improvement. Microelectron. J. 39 (2) (2008)
Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani
Performance Improvement of Physical Retiming with Shortcut Insertion. ISVLSI (2008)
Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi
FPGA-Based Circuit Model Emulation of Quantum Algorithms. ISVLSI (2008)
Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi
An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty. DSD (2008)
Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi
Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. ISVLSI (2008)
Ali Jahanian, Morteza Saheb Zamani, Mostafa Rezvani, Mehrdad Najibi
Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability. CSICC (2008)
Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani
An architecture framework for an adaptive extensible processor. J. Supercomput. 45 (3) (2008)
Ehsan K. Ardestani, Morteza Saheb Zamani, Mehdi Sedighi
A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits. DSD (2008)
Mehdi Saeedi, Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani
Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. DSD (2008)
Arash Mehdizadeh, Morteza Saheb Zamani, Hosein Shafiei
An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme. ISVLSI (2008)
Hamid Fadishei, Mehdi Saeedi, Morteza Saheb Zamani
A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems. Microprocess. Microsystems 32 (4) (2008)
Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi
Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms. ASP-DAC (2008)
Yasaman Sanaee, Mehdi Saeedi, Morteza Saheb Zamani
Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions. ISVLSI (2008)
Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami
Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. IEICE Trans. Inf. Syst. (12) (2007)
Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
A novel synthesis algorithm for reversible circuits. ICCAD (2007)
Hamid Reza Kheirabadi, Morteza Saheb Zamani
An efficient net ordering algorithm for buffer insertion. ACM Great Lakes Symposium on VLSI (2007)
Ali Jahanian, Morteza Saheb Zamani
Metro-on-chip: an efficient physical design technique for congestion reduction. IEICE Electron. Express 4 (16) (2007)
Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi
On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. ISVLSI (2007)
Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Zamani, Hossein Pedram, Farhad Mehdipour
An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. VLSI-SoC (2007)
Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian
Evaluation, prediction and reduction of routing congestion. Microelectron. J. 38 (8-9) (2007)
Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. ICESS (2007)
Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi
Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. DSD (2007)
Ali Jahanian, Morteza Saheb Zamani
Improved timing closure by early buffer planning in floor-placement design flow. ACM Great Lakes Symposium on VLSI (2007)
Hamid Reza Kheirabadi, Morteza Saheb Zamani, Mehdi Saeedi
An Efficient Analytical Approach to Path-Based Buffer Insertion. ISVLSI (2007)
Farhad Mehdipour, Morteza Saheb Zamani, H. R. Ahmadifar, Mehdi Sedighi, Kazuaki J. Murakami
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. IPDPS (2006)
Ali Jahanian, Morteza Saheb Zamani
Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. ISVLSI (2006)
Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Koji Inoue, Mehdi Sedighi
Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. EUC (2006)
Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Mehdi Sedighi, Koji Inoue
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. Asia-Pacific Computer Systems Architecture Conference (2006)
Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki J. Murakami, Hamid Noori
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. ERSA (2006)
Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian
Prediction and reduction of routing congestion. ISPD (2006)
Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani
A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. FPL (2006)
Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi
An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. Microprocess. Microsystems 30 (1) (2006)
Arash Hariri, Reza Rastegar, Keivan Navi, Morteza Saheb Zamani, Mohammad Reza Meybodi
Cellular Learning Automata based Evolutionary Computing (CLA-EC) for Intrinsic Hardware Evolution. Evolvable Hardware (2005)
Arash Hariri, Reza Rastegar, Morteza Saheb Zamani, Mohammad Reza Meybodi
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA. FCCM (2005)
Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabaei
A novel reconfigurable hardware architecture for IP address lookup. ANCS (2005)
Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi
Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. DSD (2005)
Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghian, Farhad Mehdipour
A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms. FPT (2005)

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Publication Activity (10 Years)

Top Topics

Top Venues

Morteza Saheb Zamani