Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology.
Ali JahanianMorteza Saheb ZamaniHamid SafizadehPublished in: Integr. (2011)
Keyphrases
- power consumption
- low power
- low power consumption
- power dissipation
- dynamic power management
- cmos technology
- nm technology
- power management
- single chip
- energy efficiency
- power saving
- power reduction
- low cost
- energy saving
- battery life
- high speed
- energy management
- battery powered
- real time
- data center
- clock frequency
- image sensor
- design methodology