Kia Bazargan

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 31

Top Topics

Random Number Generator

Lossless Compression

Convolutional Neural Networks

Hardware Design

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Computers

Publications

Alireza Khataei, Kia Bazargan
CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and Beyond. FPGA (2024)
Alireza Khataei, Gaurav Singh, Kia Bazargan
SimBU: Self-Similarity-Based Hybrid Binary-Unary Computing for Nonlinear Functions. IEEE Trans. Computers 73 (9) (2024)
Alireza Khataei, Kia Bazargan
Constant Coefficient Multipliers Using Self-Similarity-Based Hybrid Binary-Unary Computing. ICCAD (2023)
Alireza Khataei, Gaurav Singh, Kia Bazargan
Optimizing Hybrid Binary-Unary Hardware Accelerators Using Self-Similarity Measures. FCCM (2023)
Alireza Khataei, Gaurav Singh, Kia Bazargan
Approximate Hybrid Binary-Unary Computing with Applications in BERT Language Model and Image Processing. FPGA (2023)
S. Rasoul Faraji, Pierre Abillama, Kia Bazargan
Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15 (3) (2022)
S. Rasoul Faraji, Kia Bazargan
Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs. ICCAD (2020)
M. Hassan Najafi, S. Rasoul Faraji, Kia Bazargan, David J. Lilja
Energy-Efficient Pulse-Based Convolution for Near-Sensor Processing. ISCAS (2020)
S. Rasoul Faraji, Pierre Abillama, Kia Bazargan
Low-Cost Approximate Constant Coefficient Hybrid Binary-Unary Multiplier for DSP Applications. FCCM (2020)
S. Rasoul Faraji, Kia Bazargan
Hybrid Binary-Unary Hardware Accelerator. IEEE Trans. Computers 69 (9) (2020)
Soheil Mohajer, Zhiheng Wang, Kia Bazargan, Yuyang Li
Parallel Unary Computing Based on Function Derivatives. ACM Trans. Reconfigurable Technol. Syst. 14 (1) (2020)
Zhiheng Wang, Devan Larso, Morgen Barker, Soheil Mohajer, Kia Bazargan
Deterministic Shuffling Networks to Implement Stochastic Circuits in Parallel. IEEE Trans. Very Large Scale Integr. Syst. 28 (8) (2020)
S. Rasoul Faraji, Pierre Abillama, Gaurav Singh, Kia Bazargan
HBUCNNA: Hybrid Binary-Unary Convolutional Neural Network Accelerator. ISCAS (2020)
Sayed Abdolrasouol Faraji, Gaurav Singh, Kia Bazargan
HBUNN - Hybrid Binary-Unary Neural Network: Realizing a Complete CNN on an FPGA. ICCD (2019)
M. Hassan Najafi, S. Rasoul Faraji, Bingzhe Li, David J. Lilja, Kia Bazargan
Accelerating Deterministic Bit-Stream Computing with Resolution Splitting. ISQED (2019)
M. Hassan Najafi, S. Rasoul Faraji, Kia Bazargan, David J. Lilja
Energy-Efficient Near-Sensor Convolution using Pulsed Unary Processing. ASAP (2019)
S. Rasoul Faraji, M. Hassan Najafi, Bingzhe Li, David J. Lilja, Kia Bazargan
Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing. DATE (2019)
S. Rasoul Faraji, Kia Bazargan
Hybrid binary-unary hardware accelerator. ASP-DAC (2019)
Zhiheng Wang, Soheil Mohajer, Kia Bazargan
Low latency parallel implementation of traditionally-called stochastic circuits using deterministic shuffling networks. ASP-DAC (2018)
Soheil Mohajer, Zhiheng Wang, Kia Bazargan
Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data. FPGA (2018)
M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan
Low-Cost Sorting Network Circuits Using Unary Processing. IEEE Trans. Very Large Scale Integr. Syst. 26 (8) (2018)
Zhiheng Wang, Ryan N. Goh, Kia Bazargan, Arnd Scheel, Naman Saraf
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan
Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits. IEEE Trans. Computers 66 (10) (2017)
M. Hassan Najafi, Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel
A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing. ACM J. Emerg. Technol. Comput. Syst. 13 (4) (2017)
Naman Saraf, Kia Bazargan
A memory optimized mersenne-twister random number generator. MWSCAS (2017)
M. Hassan Najafi, Shiva Jamali-Zavareh, David J. Lilja, Marc D. Riedel, Kia Bazargan, Ramesh Harjani
An Overview of Time-Based Computing with Stochastic Constructs. IEEE Micro 37 (6) (2017)
M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan
Power and Area Efficient Sorting Networks Using Unary Processing. ICCD (2017)
M. Hassan Najafi, Shiva Jamali-Zavareh, David J. Lilja, Marc D. Riedel, Kia Bazargan, Ramesh Harjani
Time-Encoded Values for Highly Efficient Stochastic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 25 (5) (2017)
M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan
Polysynchronous stochastic circuits. ASP-DAC (2016)
Nimish Agashiwala, Satya Prakash Upadhyay, Kia Bazargan
t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only). FPGA (2016)
Naman Saraf, Kia Bazargan
Polynomial Arithmetic Using Sequential Stochastic Logic. ACM Great Lakes Symposium on VLSI (2016)
Zhiheng Wang, Naman Saraf, Kia Bazargan, Arnd Scheel
Randomness meets feedback: stochastic implementation of logistic map dynamical system. DAC (2015)
Amir Yazdanbakhsh, Divya Mahajan, Bradley Thwaites, Jongse Park, Anandhavel Nagendrakumar, Sindhuja Sethuraman, Kartik Ramkrishnan, Nishanthi Ravindran, Rudra Jariwala, Abbas Rahimi, Hadi Esmaeilzadeh, Kia Bazargan
Axilog: language support for approximate hardware design. DATE (2015)
Divya Mahajan, Kartik Ramkrishnan, Rudra Jariwala, Amir Yazdanbakhsh, Jongse Park, Bradley Thwaites, Anandhavel Nagendrakumar, Abbas Rahimi, Hadi Esmaeilzadeh, Kia Bazargan
Axilog: Abstractions for Approximate Hardware Design and Reuse. IEEE Micro 35 (5) (2015)
Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel
Computation on Stochastic Bit Streams Digital Image Processing Case Studies. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Peng Li, David J. Lilja, Weikang Qian, Marc D. Riedel, Kia Bazargan
Logical Computation on Stochastic Bit Streams with Linear Finite-State Machines. IEEE Trans. Computers 63 (6) (2014)
Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel
IIR filters using stochastic arithmetic. DATE (2014)
Yanzi Zhu, Peiran Suo, Kia Bazargan
Binary stochastic implementation of digital logic. FPGA (2014)
Naman Saraf, Kia Bazargan
Sequential logic to transform probabilities. ICCAD (2013)
Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel
Stochastic functions using sequential logic. ICCD (2013)
Peng Li, Weikang Qian, David J. Lilja, Kia Bazargan, Marc D. Riedel
Case Studies of Logical Computation on Stochastic Bit Streams. PATMOS (2012)
Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel
The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic. ICCAD (2012)
Peng Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja
The synthesis of linear Finite State Machine-based Stochastic Computational Elements. ASP-DAC (2012)
Weikang Qian, Chen Wang, Peng Li, David J. Lilja, Kia Bazargan, Marc D. Riedel
An efficient implementation of numerical integration using logical computation on stochastic bit streams. ICCAD (2012)
Hossein Omidian Savarbaghi, Kia Bazargan
FPGA placement by graph isomorphism (abstract only). FPGA (2011)
Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan, David J. Lilja
An Architecture for Fault-Tolerant Computation with Stochastic Logic. IEEE Trans. Computers 60 (1) (2011)
Pongstorn Maidee, Kia Bazargan
A fast SPFD-based rewiring technique. ASP-DAC (2010)
Pongstorn Maidee, Kia Bazargan
Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (12) (2010)
Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja
The synthesis of combinational logic to generate probabilities. ICCAD (2009)
Satish Sivaswamy, Kia Bazargan, Marc D. Riedel
Estimation and optimization of reliability of noisy digital circuits. ISQED (2009)
Seyyed Ahmad Razavi, Morteza Saheb Zamani, Kia Bazargan
A tileable switch module architecture for homogeneous 3D FPGAs. 3DIC (2009)
Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja
A reconfigurable stochastic architecture for highly reliable computing. ACM Great Lakes Symposium on VLSI (2009)
Hamid Safizadeh, Mohammad Tahghighi, Ehsan K. Ardestani, Gholamhossein Tavasoli, Kia Bazargan
Using randomization to cope with circuit uncertainty. DATE (2009)
Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan
Fast and Accurate Statistical Criticality Computation Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (3) (2009)
Hushrav Mogal, Kia Bazargan
Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. ICCAD (2008)
Pongstorn Maidee, Nagib Hakim, Kia Bazargan
FPGA family composition and effects of specialized blocks. FPL (2008)
Satish Sivaswamy, Kia Bazargan
Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 1 (1) (2008)
Satish Sivaswamy, Kia Bazargan
Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs. FPL (2007)
Hushrav Mogal, Kia Bazargan
Microarchitecture floorplanning for sub-threshold leakage reduction. DATE (2007)
Kia Bazargan, André DeHon
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (2) (2007)
Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan
Clustering based pruning for statistical criticality computation under process variations. ICCAD (2007)
Pongstorn Maidee, Kia Bazargan
A generalized and unified SPFD-based rewiring technique. FPL (2007)
Satish Sivaswamy, Kia Bazargan
Variation-aware routing for FPGAs. FPGA (2007)
Cristinel Ababei, Kia Bazargan
Non-contiguous linear placement for reconfigurable fabrics. Int. J. Embed. Syst. 2 (1/2) (2006)
Pongstorn Maidee, Kia Bazargan
Defect-Tolerant FPGA Architecture Exploration. FPL (2006)
Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh
Statistical Analysis and Design of HARP FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (10) (2006)
Cristinel Ababei, Hushrav Mogal, Kia Bazargan
Three-dimensional place and route for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
Timing-driven partitioning-based placement for island style FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (3) (2005)
Cristinel Ababei, Hushrav Mogal, Kia Bazargan
Three-dimensional place and route for FPGAs. ASP-DAC (2005)
Cristinel Ababei, Hushrav Mogal, Kia Bazargan
3D FPGAs: placement, routing, and architecture evaluation (abstract only). FPGA (2005)
Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh
HARP: hard-wired routing pattern FPGAs. FPGA (2005)
Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan
A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory. J. Comput. Sci. Technol. 20 (5) (2005)
Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar
Placement and Routing in 3D Integrated Circuits. IEEE Des. Test Comput. 22 (6) (2005)
Cristinel Ababei, Kia Bazargan
Non-Contiguous Linear Placement for Reconfigurable Fabrics. IPDPS (2004)
Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan
Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory. Asia-Pacific Computer Systems Architecture Conference (2004)
Cristinel Ababei, Pongstorn Maidee, Kia Bazargan
Exploring Potential Benefits of 3D FPGA Integration. FPL (2004)
John C. Lach, Kia Bazargan
Editorial: Special issue on dynamically adaptable embedded systems. ACM Trans. Embed. Comput. Syst. 3 (2) (2004)
Wonjoon Choi, Kia Bazargan
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration. DATE (2003)
Cristinel Ababei, Kia Bazargan
Timing Minimization by Statistical Timing hMetis-based Partitioning. VLSI Design (2003)
Cristinel Ababei, Kia Bazargan
Placement Method Targeting Predictability Robustness and Performance. ICCAD (2003)
Karthikeyan Bhasyam, Kia Bazargan
HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming. DSD (2003)
Wonjoon Choi, Kia Bazargan
Incremental Placement for Timing Optimization. ICCAD (2003)
Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
Fast timing-driven partitioning-based placement for island style FPGAs. DAC (2003)
Vamsi Krishna Marreddy, Sharareh Noorbaloochi, Kia Bazargan
Linear Placement for Static / Dynamic Reconfiguration in JBits. FCCM (2003)
Cristinel Ababei, Kia Bazargan
Statistical Timing Driven Partitioning for VLSI Circuits. DATE (2002)
Jinghuan Chen, Jaekyun Moon, Kia Bazargan
A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator. DAC (2002)
Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis
Multi-objective circuit partitioning for cutsize and path-based delay minimization. ICCAD (2002)
Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh
Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures. DAC (2001)
Abhishek Ranjan, Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh
Fast floorplanning for effective prediction and construction. IEEE Trans. Very Large Scale Integr. Syst. 9 (2) (2001)
Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh
A C to Hardware/Software Compiler. FCCM (2000)
Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh
Fast Hierarchical Floorplanning with Congestion and Timing Control. ICCD (2000)
Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. Des. Autom. Embed. Syst. 5 (3-4) (2000)
Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
Fast Template Placement for Reconfigurable Computing Systems. IEEE Des. Test Comput. 17 (1) (2000)
Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh
Fast and accurate estimation of floorplans in logic/high-level synthesis. ACM Great Lakes Symposium on VLSI (2000)
Kia Bazargan, Samjung Kim, Majid Sarrafzadeh
Nostradamus: a floorplanner of uncertain designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (4) (1999)
Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. IEEE International Workshop on Rapid System Prototyping (1999)
Kia Bazargan, Samjung Kim, Majid Sarrafzadeh
Nostradamus: a floorplanner of uncertain design. ISPD (1998)