Elham Cheshmikhani

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 17

Top Topics

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Computers

Publications

Elham Cheshmikhani, Fateme Shokouhinia, Hamed Farbeh
A Low-Cost Fault-Tolerant Racetrack Cache Based on Data Compression. IEEE Trans. Circuits Syst. II Express Briefs 71 (8) (2024)
Biagio Peccerillo, Elham Cheshmikhani, Mirco Mannino, Andrea Mondelli, Sandro Bartolini
IXIAM: ISA EXtension for Integrated Accelerator Management. IEEE Access 11 (2023)
Elham Cheshmikhani, Hamed Farbeh, Seyed Ghassem Miremadi, Hossein Asadi
TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches. CoRR (2022)
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison. IEEE Trans. Computers 71 (6) (2022)
Elham Cheshmikhani, Biagio Peccerillo, Andrea Mondelli, Sandro Bartolini
A General Framework for Accelerator Management Based on ISA Extension. IEEE Access 10 (2022)
Mostafa Hadizadeh, Elham Cheshmikhani, Maysam Rahmanpour, Onur Mutlu, Hossein Asadi
CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers. IEEE Trans. Parallel Distributed Syst. 33 (10) (2022)
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches. CoRR (2022)
Mostafa Hadizadeh, Elham Cheshmikhani, Maysam Rahmanpour, Onur Mutlu, Hossein Asadi
CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers. CoRR (2022)
Mostafa Hadizadeh, Elham Cheshmikhani, Hossein Asadi
STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation. DATE (2020)
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches. IEEE Trans. Reliab. 69 (2) (2020)
Elham Cheshmikhani, Hamed Farbeh, Seyed Ghassem Miremadi, Hossein Asadi
TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches. IEEE Trans. Computers 68 (3) (2019)
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches. ASP-DAC (2019)
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation. DATE (2019)
Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Ensieh Aliagha, Elham Cheshmikhani
A-CACHE: Alternating Cache Allocation to Conduct Higher Endurance in NVM-Based Caches. IEEE Trans. Circuits Syst. II Express Briefs (7) (2019)
Shahab Shoar, Hamid R. Zarandi, Farnad Nasirzadeh, Elham Cheshmikhani
Fast Fault Tree Analysis for Hybrid Uncertainties Using Stochastic Logic Implemented on Field-Programmable Gate Arrays: An Application in Quantitative Assessment and mitigation of Welding Defects Risk. Qual. Reliab. Eng. Int. 33 (7) (2017)
Elham Cheshmikhani, Amir Mahdi Hosseini Monazzah, Hamed Farbeh, Seyed Ghassem Miremadi
Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches. EDCC (2016)
Elham Cheshmikhani, Hamid R. Zarandi
Accelerating Dynamic Fault Tree Analysis Based on Stochastic Logic Utilizing GPGPUs. PDP (2016)
Elham Cheshmikhani, Hamid R. Zarandi
Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates. Microelectron. Reliab. 55 (11) (2015)