Sandro Bartolini

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 19

Top Topics

Lessons Learned

Top Venues

Concurr. Comput. Pract. Exp.

ACM J. Emerg. Technol. Comput. Syst.

Publications

Mirco Mannino, Yinting Huang, Biagio Peccerillo, Alessio Medaglini, Sandro Bartolini
Integration of RISC-V Page Table Walk in gem5 SE Mode. RAPIDO@HiPEAC (2024)
Mirco Mannino, Biagio Peccerillo, Andrea Mondelli, Sandro Bartolini
Analysis and Optimization of Direct Convolution Execution on Multi-Core Processors. IEEE Access 11 (2023)
Biagio Peccerillo, Elham Cheshmikhani, Mirco Mannino, Andrea Mondelli, Sandro Bartolini
IXIAM: ISA EXtension for Integrated Accelerator Management. IEEE Access 11 (2023)
Davide Privitera, Stefano Bellissima, Sandro Bartolini
Adaptive Dosing Control System Through ARIMA Model for Peristaltic Pumps. IEEE Access 11 (2023)
Alessio Medaglini, Sandro Bartolini, Gianluca Mandò, Eduardo Quiñones, Sara Royuela
Software-Based Fault-Detection Technique for Object Tracking in Autonomous Vehicles. MECO (2023)
Mirco Mannino, Biagio Peccerillo, Andrea Mondelli, Sandro Bartolini
Energy and Performance Improvements for Convolutional Accelerators Using Lightweight Address Translation Support. CF (2023)
Pablo Antonio Martínez, Biagio Peccerillo, Sandro Bartolini, José M. García, Gregorio Bernabé
Applying Intel's oneAPI to a machine learning case study. Concurr. Comput. Pract. Exp. 34 (13) (2022)
Biagio Peccerillo, Sandro Bartolini
Flexible task-DAG management in PHAST library: Data-parallel tasks and orchestration support for heterogeneous systems. Concurr. Comput. Pract. Exp. 34 (2) (2022)
Elham Cheshmikhani, Biagio Peccerillo, Andrea Mondelli, Sandro Bartolini
A General Framework for Accelerator Management Based on ISA Extension. IEEE Access 10 (2022)
Biagio Peccerillo, Mirco Mannino, Andrea Mondelli, Sandro Bartolini
A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives. J. Syst. Archit. 129 (2022)
Pablo Antonio Martínez, Biagio Peccerillo, Sandro Bartolini, José M. García, Gregorio Bernabé
Performance portability in a real world application: PHAST applied to Caffe. Int. J. High Perform. Comput. Appl. 36 (3) (2022)
Eduardo José Gómez-Hernández, Pablo Antonio Martínez, Biagio Peccerillo, Sandro Bartolini, José Manuel García Carrasco, Gregorio Bernabé
Using PHAST to port Caffe library: First experiences and lessons learned. CoRR (2020)
Biagio Peccerillo, Sandro Bartolini, Çetin Kaya Koç
Parallel bitsliced AES through PHAST: a single-source high-performance library for multi-cores and GPUs. J. Cryptogr. Eng. 9 (2) (2019)
Biagio Peccerillo, Sandro Bartolini
Task-DAG Support in Single-Source PHAST Library: Enabling Flexible Assignment of Tasks to CPUs and GPUs in Heterogeneous Architectures. PMAM@PPoPP (2019)
Biagio Peccerillo, Sandro Bartolini
PHAST - A Portable High-Level Modern C++ Programming Library for GPUs and Multi-Cores. IEEE Trans. Parallel Distributed Syst. 30 (1) (2019)
Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete
Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems. Future Gener. Comput. Syst. 78 (2018)
Sandro Bartolini, Alessandro Mecocci, Alessandro Pozzebon, Claudia Zoppetti, Duccio Bertoni, Giovanni Sarti, Andrea Caiti, Riccardo Costanzi, Filippo Catani, Andrea Ciampalini, Sandro Moretti
Augmented Virtuality for Coastal Management: A Holistic Use of In Situ and Remote Sensing for Large Scale Definition of Coastal Dynamics. ISPRS Int. J. Geo Inf. 7 (3) (2018)
Paolo Grani, Sandro Bartolini
Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPs. ACM J. Emerg. Technol. Comput. Syst. 14 (1) (2018)
Biagio Peccerillo, Sandro Bartolini
PHAST Library - Enabling Single-Source and High Performance Code for GPUs and Multi-cores. HPCS (2017)
Paolo Grani, Robert Hendry, Sandro Bartolini, Keren Bergman
Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects. ICNC (2015)
Paolo Grani, Sandro Bartolini
Design Options for Optical Ring Interconnect in Future Client Devices. ACM J. Emerg. Technol. Comput. Syst. 10 (4) (2014)
Luca Ramini, Hervé Tatenguem Fankem, Alberto Ghiribaldi, Paolo Grani, Marta Ortín-Obón, Anja Boos, Sandro Bartolini
Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems. NOCS (2014)
Paolo Grani, Sandro Bartolini
Simultaneous Optical Path-Setup for Reconfigurable Photonic Networks in Tiled CMPs. HPCC/CSS/ICESS (2014)
Sandro Bartolini, Iacopo Casini, Paolo Detti
Solving Graph Partitioning Problems Arising in Tagless Cache Management. ISCO (2014)
Antonio García-Guirado, Ricardo Fernández Pascual, José M. García, Sandro Bartolini
Managing resources dynamically in hybrid photonic-electronic networks-on-chip. Concurr. Comput. Pract. Exp. 26 (15) (2014)
Sandro Bartolini, José M. García
Exploiting silicon photonics for energy-efficient heterogeneous parallel architectures. Concurr. Comput. Pract. Exp. 26 (15) (2014)
Luca Ramini, Alberto Ghiribaldi, Paolo Grani, Sandro Bartolini, Hervé Tatenguem Fankem, Davide Bertozzi
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline. DATE (2014)
Sandro Bartolini, Luca Lusnig, Enrico Martinelli
Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip Multiprocessors. DSD (2013)
Luca Ramini, Paolo Grani, Sandro Bartolini, Davide Bertozzi
Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis. DATE (2013)
Sandro Bartolini, Paolo Grani
Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs. MES (2013)
Sandro Bartolini, Paolo Grani
A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs. DSD (2012)
Timothy M. Jones, Sandro Bartolini, Jonas Maebe, Dominique Chanet
Link-time optimization for power efficiency in a tagless instruction cache. CGO (2011)
Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete
Eighth MEDEA Workshop. Trans. High Perform. Embed. Archit. Compil. 3 (2011)
Sandro Bartolini, Pierfrancesco Foglia, Marco Solinas, Cosimo Antonio Prete
Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs. SBAC-PAD (2010)
Timothy M. Jones, Sandro Bartolini, Bruno De Bus, John Cavazos, Michael F. P. O'Boyle
Instruction Cache Energy Saving Through Compiler Way-Placement. DATE (2008)
Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli
). IEEE Trans. Computers 57 (5) (2008)
Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete
MEmory performance: DEaling with applications, systems and architecture. SIGARCH Comput. Archit. News 35 (4) (2007)
Sandro Bartolini, Cinzia Castagnini, Enrico Martinelli
Inclusion of a Montgomery Multiplier Unit into an Embedded Processor's Datapath to Speed-up Elliptic Curve Cryptography. IAS (2007)
Sandro Bartolini, Roberto Giorgi
Issues in Embedded Single-Chip Multicore Architectures. J. Embed. Comput. 2 (2) (2006)
Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
Memory performance: dealing with applications, systems and architecture. SIGARCH Comput. Archit. News 34 (1) (2006)
Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete
Embedded processors and systems: Architectural issues and solutions for emerging applications. J. Embed. Comput. 2 (1) (2006)
Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete
Guests editor's introduction. SIGARCH Comput. Archit. News 33 (3) (2005)
Sandro Bartolini, Cosimo Antonio Prete
Optimizing instruction cache performance of embedded systems. ACM Trans. Embed. Comput. Syst. 4 (4) (2005)
Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli
A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields. SBAC-PAD (2004)
Sandro Bartolini, Cosimo Antonio Prete
A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications. SIGARCH Comput. Archit. News 32 (3) (2004)
Sandro Bartolini, Cosimo Antonio Prete
A cache-aware program transformation technique suitable for embedded systems. Inf. Softw. Technol. 44 (13) (2002)
Sandro Bartolini, Roberto Giorgi, Jelica Protic, Cosimo Antonio Prete, Mateo Valero
Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. SIGARCH Comput. Archit. News 29 (5) (2001)
Sandro Bartolini, Cosimo Antonio Prete
An Object Level Transformation Technique to Improve the Performance of Embedded Applications. SCAM (2001)