Roberto Giorgi

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 27

Top Topics

Execution Model

Embedded Systems

Top Venues

Microprocess. Microsystems

Conf. Computing Frontiers

Publications

Marco Procaccini, Amin Sahebi, Marco Barbone, Wayne Luk, Georgi Gaydadjiev, Roberto Giorgi
Accelerating Large-Scale Graph Processing with FPGAs: Lesson Learned and Future Directions. PARMA-DITAM (2024)
Amin Sahebi, Marco Barbone, Marco Procaccini, Wayne Luk, Georgi Gaydadjiev, Roberto Giorgi
Distributed large-scale graph processing on FPGAs. J. Big Data 10 (1) (2023)
Roberto Giorgi
Extending Performance and Reliability via Modular FPGA Clusters. MECO (2022)
Gianfranco Mariotti, Roberto Giorgi
WebRISC-V: A 32/64-bit RISC-V pipeline simulation tool. SoftwareX 18 (2022)
Marco Aldinucci, Giovanni Agosta, Antonio Andreini, Claudio Agostino Ardagna, Andrea Bartolini, Alessandro Cilardo, Biagio Cosenza, Marco Danelutto, Roberto Esposito, William Fornaciari, Roberto Giorgi, Davide Lengani, Raffaele Montella, Mauro Olivieri, Sergio Saponara, Daniele Simoni, Massimo Torquati
The Italian research on HPC key technologies across EuroHPC. CF (2021)
Antonio Filgueras, Miquel Vidal, Marc Mateu, Daniel Jiménez-González, Carlos Álvarez, Xavier Martorell, Eduard Ayguadé, Dimitrios Theodoropoulos, Dionisios N. Pnevmatikatos, Paolo Gai, Stefano Garzarella, David Oro, Javier Hernando, Nicola Bettin, Alberto Pomella, Marco Procaccini, Roberto Giorgi
The AXIOM Project: IoT on Heterogeneous Embedded Platforms. IEEE Des. Test 38 (5) (2021)
Roberto Giorgi, Marco Procaccini, Amin Sahebi
DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model. ARCS (2021)
Roberto Giorgi, Nicola Bettin, Sara Ermini, Francesco Montefoschi, Antonio Rizzo
An Iris+Voice Recognition System for a Smart Doorbell. MECO (2019)
Roberto Giorgi, David Oro, Sara Ermini, Francesco Montefoschi, Antonio Rizzo
Embedded Face Analysis for Smart Videosurveillance. MECO (2019)
Lorenzo Verdoscia, Amin Sahebi, Roberto Giorgi
A Data-Flow Methodology for Accelerating FFT. MECO (2019)
Roberto Giorgi, Marco Procaccini
Bridging a Data-Flow Execution Model to a Lightweight Programming Model. HPCS (2019)
Roberto Giorgi, Marco Procaccini, Farnam Khalili
Analyzing the Impact of Operating System Activity of Different Linux Distributions in a Distributed Environment. PDP (2019)
Roberto Giorgi, Marco Procaccini, Farnam Khalili
A Design Space Exploration Tool Set for Future 1K-core High-Performance Computers. RAPIDO (2019)
Roberto Giorgi, Gianfranco Mariotti
WebRISC-V: a Web-Based Education-Oriented RISC-V Pipeline Simulation Environment. WCAE@ISCA (2019)
Roberto Giorgi, Farnam Khalili, Marco Procaccini
Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise - Designing a Computer Architecture via HLS). Int. J. Reconfigurable Comput. 2019 (2019)
Roberto Giorgi, Marco Procaccini, Farnam Khalili
AXIOM: A Scalable, Efficient and Reconfigurable Embedded Platform. DATE (2019)
Roberto Giorgi, Farnam Khalili, Marco Procaccini
Energy Efficiency Exploration on the ZYNQ Ultrascale+. ICM (2018)
Roberto Giorgi
Scalable embedded computing through reconfigurable hardware: Comparing DF-Threads, cilk, openmpi and jump. Microprocess. Microsystems 63 (2018)
Dimitris Theodoropoulos, Somnath Mazumdar, Eduard Ayguadé, Nicola Bettin, Javier Bueno, Sara Ermini, Antonio Filgueras, Daniel Jiménez-González, Carlos Álvarez-Martínez, Xavier Martorell, Francesco Montefoschi, David Oro, Dionisis N. Pnevmatikatos, Antonio Rizzo, Paolo Gai, Stefano Garzarella, Bruno Morelli, Alberto Pomella, Roberto Giorgi
The AXIOM platform for next-generation cyber physical systems. Microprocess. Microsystems 52 (2017)
Roberto Giorgi
AXIOM: A 64-bit reconfigurable hardware/software platform for scalable embedded computing. MECO (2017)
Roberto Giorgi
Chapter Two - Exploring Future Many-Core Architectures: The TERAFLUX Evaluation Framework. Adv. Comput. 104 (2017)
Antonio Rizzo, Francesco Montefoschi, Maurizio Caporali, Antonio Gisondi, Giovanni Burresi, Roberto Giorgi
Rapid prototyping IoT solutions based on Machine Learning. ECCE (2017)
Roberto Giorgi
AXIOM: A 64-bit reconfigurable hardware/software platform for scalable embedded computing. MECO (2017)
Somnath Mazumdar, Eduard Ayguadé, Nicola Bettin, Javier Bueno, Sara Ermini, Antonio Filgueras, Daniel Jiménez-González, Carlos Álvarez-Martínez, Xavier Martorell, Francesco Montefoschi, David Oro, Dionisios N. Pnevmatikatos, Antonio Rizzo, Dimitris Theodoropoulos, Roberto Giorgi
AXIOM: A Hardware-Software Platform for Cyber Physical Systems. DSD (2016)
Antonio Rizzo, Giovanni Burresi, Francesco Montefoschi, Maurizio Caporali, Roberto Giorgi
Making IoT with UDOO. IxD&A 30 (2016)
Roberto Giorgi
Exploring dataflow-based thread level parallelism in cyber-physical systems. Conf. Computing Frontiers (2016)
Sebastian Weis, Arne Garbade, Bernhard Fechner, Avi Mendelson, Roberto Giorgi, Theo Ungerer
Architectural Support for Fault Tolerance in a Teradevice Dataflow System. Int. J. Parallel Program. 44 (2) (2016)
Giovanni Burresi, Roberto Giorgi
A field experience for a vehicle recognition system using magnetic sensors. MECO (2015)
Lorenzo Verdoscia, Roberto Vaccaro, Roberto Giorgi
A matrix multiplier case study for an evaluation of a configurable dataflow-machine. Conf. Computing Frontiers (2015)
Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos, Carlos Álvarez, Eduard Ayguadé, Javier Bueno, Antonio Filgueras, Daniel Jiménez-González, Xavier Martorell, Nacho Navarro, Carlos Segura, Carles Fernández, David Oro, Javier Rodríguez Saeta, Paolo Gai, Antonio Rizzo, Roberto Giorgi
The AXIOM project (Agile, eXtensible, fast I/O Module). SAMOS (2015)
Carlos Álvarez, Eduard Ayguadé, Javier Bueno, Antonio Filgueras, Daniel Jiménez-González, Xavier Martorell, Nacho Navarro, Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos, Davide Catani, Claudio Scordino, Paolo Gai, Carlos Segura, Carles Fernández, David Oro, Javier Rodríguez Saeta, Pierluigi Passera, Alberto Pomella, Antonio Rizzo, Roberto Giorgi
The AXIOM Software Layers. DSD (2015)
Stefan Wesner, Lutz Schubert, Rosa M. Badia, Antonio Rubio, Pier Stanislao Paolucci, Roberto Giorgi
Special Section on Terascale Computing. Future Gener. Comput. Syst. 53 (2015)
Roberto Giorgi
Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing. EUC (2015)
Roberto Giorgi, Alberto Scionti
A scalable thread scheduling co-processor based on data-flow principles. Future Gener. Comput. Syst. 53 (2015)
Nam Ho, Andrea Mondelli, Alberto Scionti, Marco Solinas, Antoni Portero, Roberto Giorgi
Enhancing an x86_64 multi-core architecture with data-flow execution support. Conf. Computing Frontiers (2015)
Andrea Mondelli, Nam Ho, Alberto Scionti, Marco Solinas, Antoni Portero, Roberto Giorgi
Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions. DSD (2015)
Roberto Giorgi, Paolo Faraboschi
An Introduction to DF-Threads and their Execution Model. SBAC-PAD (Workshops) (2014)
Alberto Scionti, Stamatios Kavvadias, Roberto Giorgi
Dynamic power reduction in self-adaptive embedded systems through benchmark analysis. MECO (2014)
Roberto Giorgi, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Rahulkumar Gayatri, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Joshua Landwehr, Nhat Minh Lê, Feng Li, Mikel Luján, Avi Mendelson, Laurent Morin, Nacho Navarro, Tomasz Patejko, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Ian Watson, Sebastian Weis, Stéphane Zuckerman, Mateo Valero
TERAFLUX: Harnessing dataflow in next generation teradevices. Microprocess. Microsystems 38 (8) (2014)
Irina Branovic, Ranko Popovic, Nenad Jovanovic, Roberto Giorgi, Bosko Nikolic, Miodrag Zivkovic
Integration of simulators in virtual 3D computer science classroom. EDUCON (2014)
Marco Solinas, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Feng Li, Mikel Luján, Laurent Morin, Avi Mendelson, Nacho Navarro, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Mateo Valero, Sebastian Weis, Ian Watson, Stéphane Zuckerman, Roberto Giorgi
The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices. DSD (2013)
Antoni Portero, Alberto Scionti, Zhibin Yu, Paolo Faraboschi, Caroline Concatto, Luigi Carro, Arne Garbade, Sebastian Weis, Theo Ungerer, Roberto Giorgi
Simulating the future kilo-x86-64 core processors and their infrastructure. SpringSim (ANSS) (2012)
Stephan Wong, Luigi Carro, Stamatios Kavvadias, Georgios Keramidas, Francesco Papariello, Claudio Scordino, Roberto Giorgi, Stefanos Kaxiras
Embedded reconfigurable architectures. CASES (2012)
Roberto Giorgi
TERAFLUX: exploiting dataflow parallelism in teradevices. Conf. Computing Frontiers (2012)
Antoni Portero, Zhibin Yu, Roberto Giorgi
TERAFLUX: Exploiting Tera-device Computing Challenges. FET (2011)
Massimo Alioto, Paolo Bennati, Roberto Giorgi
Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed. ISCAS (2010)
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture. SAMOS (2009)
Kyriakos Stavrou, Demos Pavlou, Marios Nikolaides, Panayiotis Petrides, Paraskevas Evripidou, Pedro Trancoso, Zdravko Popovic, Roberto Giorgi
Programming Abstractions and Toolchain for Dataflow Multithreading Architectures. ISPDC (2009)
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture. IPDPS (2009)
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
Introducing Hardware TLP Support in the Cell Processor. CISIS (2009)
Roberto Giorgi, Paolo Bennati
Reducing Leakage through Filter Cache. DSD (2008)
Roberto Giorgi, Paolo Bennati
Filtering drowsy instruction cache to achieve better efficiency. SAC (2008)
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, Arnaldo Azevedo, Ben H. H. Juurlink
Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture. DSD (2008)
Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli
). IEEE Trans. Computers 57 (5) (2008)
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems. SBAC-PAD (2007)
Roberto Giorgi, Paolo Bennati
Reducing leakage in power-saving capable caches for embedded systems by using a filter cache. MEDEA@PACT (2007)
Sandro Bartolini, Roberto Giorgi
Issues in Embedded Single-Chip Multicore Architectures. J. Embed. Comput. 2 (2) (2006)
Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
Memory performance: dealing with applications, systems and architecture. SIGARCH Comput. Archit. News 34 (1) (2006)
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload. J. Parallel Distributed Comput. 65 (3) (2005)
Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli
A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields. SBAC-PAD (2004)
Irina Branovic, Roberto Giorgi, Enrico Martinelli
A workload characterization of elliptic curve cryptography methods in embedded environments. SIGARCH Comput. Archit. News 32 (3) (2004)
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
Speeding-up multiprocessors running DBMS workloads through coherence protocols. Int. J. High Perform. Comput. Netw. 1 (1/2/3) (2004)
Irina Branovic, Roberto Giorgi, Enrico Martinelli
WebMIPS: a new web-based MIPS simulation environment for computer architecture education. WCAE (2004)
Irina Branovic, Roberto Giorgi, Cosimo Antonio Prete
Web-based training on computer architecture: the case for JCachesim. WCAE (2002)
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture. NETWORKING Workshops (2002)
Sandro Bartolini, Roberto Giorgi, Jelica Protic, Cosimo Antonio Prete, Mateo Valero
Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. SIGARCH Comput. Archit. News 29 (5) (2001)
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications. PDCS (2001)
Krishna M. Kavi, Roberto Giorgi, Joseph Arul
Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation. IEEE Trans. Computers 50 (8) (2001)
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload. HICSS (2001)
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
Execution and Cache Performance of the Scheduled Dataflow Architecture. J. Univers. Comput. Sci. 6 (10) (2000)
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
Performance Analysis of Electronic Commerce Multiprocessor Server. HICSS (2000)
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
Process Migration Effects on Memory Performance of Multiprocessor. HiPC (1999)
Roberto Giorgi, Cosimo Antonio Prete
PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. 10 (7) (1999)
Roberto Giorgi, Cosimo Antonio Prete
An educational environment for designing and performance tuning of embedded systems. WCAE@ISCA (1998)
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
Analysis of Sharing Overhead in Shared Memory Multiprocessors. HICSS (7) (1998)
Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi
Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors. IEEE Concurrency 5 (4) (1997)
Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina
Cache memory design for embedded systems based on program locality analysis. MSE (1997)
Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi
A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors. HICSS (1) (1997)
Roberto Giorgi, Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina
A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. EUROMICRO (1996)