Arnaldo Azevedo

Publication Activity (10 Years)

Years Active: 2003-2013
Publications (10 Years): 0

Top Topics

Motion Compensation

High Throughput

Distributed Architecture

Top Venues

J. Real Time Image Process.

Publications

Bruno Zatt, Leandro M. de L. Silva, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi
A reduced memory bandwidth and high throughput HDTV motion compensation decoder for H.264/AVC High 4: 2: 2 profile. J. Real Time Image Process. 8 (1) (2013)
Kees Goossens, Arnaldo Azevedo, Karthik Chandrasekar, Manil Dev Gomony, Sven Goossens, Martijn Koedam, Yonghui Li, Davit Mirzoyan, Anca Mariana Molnos, Ashkan Beyranvand Nejad, Andrew Nelson, Shubhendu Sinha
Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow. SIGBED Rev. 10 (3) (2013)
Arnaldo Azevedo, Bart Vermeulen, Kees Goossens
Architecture and design flow for a debug event distribution interconnect. ICCD (2012)
Arnaldo Azevedo, Ben H. H. Juurlink, Cor Meenderinck, Andrei Sergeevich Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez, Mateo Valero
A Highly Scalable Parallel Implementation of H.264. Trans. High Perform. Embed. Archit. Compil. 4 (2011)
Arnaldo Azevedo, Ben H. H. Juurlink
An Instruction to Accelerate Software Caches. ARCS (2011)
Arnaldo Azevedo, Ben H. H. Juurlink
A Multidimensional Software Cache for Scratchpad-Based Systems. Int. J. Embed. Real Time Commun. Syst. 1 (4) (2010)
Alex Ramírez, Felipe Cabarcas, Ben H. H. Juurlink, Mauricio Alvarez, Friman Sánchez, Arnaldo Azevedo, Cor Meenderinck, Catalin Bogdan Ciobanu, Sebastián Isaza, Georgi Gaydadjiev
The SARC Architecture. IEEE Micro 30 (5) (2010)
Cor Meenderinck, Arnaldo Azevedo, Ben H. H. Juurlink, Mauricio Alvarez, Alex Ramírez
Parallel Scalability of Video Decoders. J. Signal Process. Syst. 57 (2) (2009)
Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Andrei Sergeevich Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez
Parallel H.264 Decoding on an Embedded Multicore Processor. HiPEAC (2009)
Arnaldo Azevedo, Ben H. H. Juurlink
An efficient software cache for H.264 motion compensation. SoC (2009)
Mauricio Alvarez, Alex Ramírez, Mateo Valero, Arnaldo Azevedo, Cor Meenderinck
Evaluación del rendimiento paralelo en el nivel macro bloque del decodificador H.264 en una arquitectura multiprocesador cc-NUMA. Rev. Avances en Sistemas Informática 6 (1) (2009)
Mauricio Alvarez Mesa, Alex Ramírez, Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mateo Valero
Scalability of Macroblock-level Parallelism for H.264 Decoding. ICPADS (2009)
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, Arnaldo Azevedo, Ben H. H. Juurlink
Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture. DSD (2008)
Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mauricio Alvarez, Alex Ramírez
Analysis of video filtering on the cell processor. ISCAS (2008)
Vagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger Endrigo Carvalho Porto, Luciano Volcan Agostini, Sergio Bampi, Altamiro Amadeu Susin
FPGA Prototyping Strategy for a H.264/AVC Video Decoder. IEEE International Workshop on Rapid System Prototyping (2007)
Bruno Zatt, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi
Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder. ISVLSI (2007)
Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi
MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV. ISCAS (2007)
Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana Gadelha Serra dos Santos, Sergio Bampi, Altamiro Amadeu Susin
FPGA Design of A H.264/AVC Main Profile Decoder for HDTV. FPL (2006)
Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi
Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV. VLSI-SoC (2006)
Arnaldo Azevedo, Luciano Volcan Agostini, Flávio Rech Wagner, Sergio Bampi
Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units. IEEE International Workshop on Rapid System Prototyping (2005)
Rodrigo Soares, Ivan Saraiva Silva, Arnaldo Azevedo
When reconfigurable architecture meets network-on-chip. SBCCI (2004)
Rodrigo Soares, Arnaldo Azevedo, Ivan Saraiva Silva
X4CP32: A New Parallel/Reconfigurable General-Purpose Processor. SBAC-PAD (2003)
Arnaldo Azevedo, Rodrigo Soares, Ivan Saraiva Silva
A New Hybrid Parallel/Reconfigurable Architecture: The X4CP32. SBCCI (2003)
Rodrigo Soares, Arnaldo Azevedo, Ivan Saraiva Silva
X4CP32: A Coarse Grain General Purpose Reconfigurable Microprocessor. IPDPS (2003)