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Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units.
Arnaldo Azevedo
Luciano Volcan Agostini
Flávio Rech Wagner
Sergio Bampi
Published in:
IEEE International Workshop on Rapid System Prototyping (2005)
Keyphrases
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reconfigurable architecture
systolic array
level parallelism
data flow
parallel architecture
distributed memory
database machines
information systems
multiprocessor systems
optimal assignment
data mining
pattern recognition
parallel processing
linear array