Bart Vermeulen

Publication Activity (10 Years)

Years Active: 1999-2021
Publications (10 Years): 6

Top Topics

Architectural Design

Eliminate Redundant

Error Detection

Safety Critical

Top Venues

Publications

Alessandro Frigerio, Bart Vermeulen, Kees G. W. Goossens
Automotive Architecture Topologies: Analysis for Safety-Critical Autonomous Vehicle Applications. IEEE Access 9 (2021)
Alessandro Frigerio, Bart Vermeulen, Kees Goossens
Isolation of redundant and mixed-critical automotive applications: effects on the system architecture. VTC Spring (2021)
Tjerk Bijlsma, Andrii Buriachevskyi, Alessandro Frigerio, Yuting Fu, Kees Goossens, Ali Osman Örs, Pieter J. van der Perk, Andrei Sergeevich Terechko, Bart Vermeulen
A Distributed Safety Mechanism using Middleware and Hypervisors for Autonomous Vehicles. DATE (2020)
Alessandro Frigerio, Bart Vermeulen, Kees Goossens
Component-Level ASIL Decomposition for Automotive Architectures. DSN Workshops (2019)
Alessandro Frigerio, Bart Vermeulen, Kees Goossens
A Generic Method for a Bottom-Up ASIL Decomposition. SAFECOMP (2018)
Abhijit K. Deb, Bart Vermeulen, Luc van Dijk
Overview of Health Monitoring Techniques for Reliability. ERMAVSS@DATE (2016)
Alexander Kordes, Bart Vermeulen, Abhijit K. Deb, Michael G. Wahl
Startup error detection and containment to improve the robustness of hybrid FlexRay networks. DATE (2014)
Sujan Pandey, Bart Vermeulen
Transient errors resiliency analysis technique for automotive safety critical applications. DATE (2014)
Arnaldo Azevedo, Bart Vermeulen, Kees Goossens
Architecture and design flow for a debug event distribution interconnect. ICCD (2012)
Thijs Schenkelaars, Bart Vermeulen, Kees Goossens
Optimal scheduling of switched FlexRay networks. DATE (2011)
Bart Vermeulen, Kees Goossens
Interactive Debug of SoCs with Multiple Clocks. IEEE Des. Test Comput. 28 (3) (2011)
Timon D. ter Braak, S. T. Burgess, H. Hurskainen, Hans G. Kerkhoff, Bart Vermeulen, Xiao Zhang
On-line dependability enhancement of multiprocessor SoCs by resource management. SoC (2010)
Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism. DSD (2010)
Bart Vermeulen, Kees Goossens
Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks. HLDVT (2010)
Bart Vermeulen, Peter Goos, Martina Vandebroek
Obtaining more information from conjoint experiments by best-worst choices. Comput. Stat. Data Anal. 54 (6) (2010)
Erik Larsson, Bart Vermeulen, Kees Goossens
A distributed architecture to check global properties for post-silicon debug. ETS (2010)
Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism. ETS (2010)
Andreas Eckel, Paul Milbredt, Zaid Al-Ars, Stefan Schneele, Bart Vermeulen, György Csertán, Christoph Scheerer, Neeraj Suri, Abdelmajid Khelil, Gerhard Fohler
INDEXYS, a Logical Step beyond GENESYS. SAFECOMP (2010)
Paul Milbredt, Bart Vermeulen, Gökhan Tabanoglu, Martin Lukasiewycz
Switched FlexRay: Increasing the effective bandwidth and safety of FlexRay networks. ETFA (2010)
Willem W. Verstraeten, Bart Vermeulen, Jan Stuckens, Stefaan Lhermitte, Dimitry Van der Zande, Marc Van Ranst, Pol Coppin
Webcams for Bird Detection and Monitoring: A Demonstration Study. Sensors 10 (4) (2010)
Kees Goossens, Bart Vermeulen, Ashkan Beyranvand Nejad
A high-level debug environment for communication-centric debug. DATE (2009)
Jeroen Geuzebroek, Bart Vermeulen
Integration of Hardware Assertions in Systems-on-Chip. ITC (2008)
Bart Vermeulen, Neal Stollon, Rolf Kühnis, Gary Swoboda, Jeff Rearick
Overview of Debug Standardization Activities. IEEE Des. Test Comput. 25 (3) (2008)
Bart Vermeulen
Functional Debug Techniques for Embedded Systems. IEEE Des. Test Comput. 25 (3) (2008)
Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat, Paul Wielage, Sebastien Mouy, Bart Vermeulen, Marc J. M. Heijligers
Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis. IEEE J. Solid State Circuits 43 (1) (2008)
Miron Abramovici, Kees Goossens, Bart Vermeulen, Jack Greenbaum, Neal Stollon, Adam Donlin
You can catch more bugs with transaction level honey. CODES+ISSS (2008)
Bart Vermeulen, Kees Goossens, Siddharth Umrani
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip. NOCS (2008)
Bart Vermeulen, Sjaak Bakker
Debug architecture for the En-II system chip. IET Comput. Digit. Tech. 1 (6) (2007)
Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek
Transaction-Based Communication-Centric Debug. NOCS (2007)
Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek
Communication-Centric SoC Debug Using Transactions. ETS (2007)
Udaya Seshua, Nagaraju Bussa, Bart Vermeulen
A Run-Time Memory Protection Methodology. ASP-DAC (2007)
Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen
Optimal Interconnect ATPG Under a Ground-Bounce Constraint. J. Electron. Test. 21 (1) (2005)
Kees van Kaam, Bart Vermeulen, Henk Jan Bergveld
Test and debug features of the RTO7 chip. ITC (2005)
Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel
Automatic generation of breakpoint hardware for silicon debug. DAC (2004)
Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge
Trends in Testing Integrated Circuits. ITC (2004)
Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen
Optimal Interconnect ATPG Under a Ground-Bounce Constraint. ITC (2003)
Sandeep Kumar Goel, Bart Vermeulen
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. J. Electron. Test. 19 (4) (2003)
Bart Vermeulen, John Dielissen, Kees Goossens, Calin Ciordas
Bringing communication networks on a chip: test and verification implications. IEEE Commun. Mag. 41 (9) (2003)
Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts
Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. IEEE Des. Test Comput. 20 (2) (2003)
Bart Vermeulen, Tom Waayers, Sjaak Bakker
Multi-TAP Controller Architecture for Digital System Chips. J. Electron. Test. 19 (4) (2003)
Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller
Creating Value Through Test. DATE (2003)
Bart Vermeulen, Sandeep Kumar Goel
Design for Debug: Catching Design Errors in Digital Chips. IEEE Des. Test Comput. 19 (3) (2002)
Bart Vermeulen, Tom Waayers, Sjaak Bakker
EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. ITC (2002)
Bart Vermeulen
TAPS All Over My Chips! So Now What Do I Do? ITC (2002)
Sandeep Kumar Goel, Bart Vermeulen
Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. ITC (2002)
Sandeep Kumar Goel, Bart Vermeulen
Data invalidation analysis for scan-based debug on multiple-clock system chips. ETW (2002)
Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel
Core-Based Scan Architecture for Silicon Debug. ITC (2002)
Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark
Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? VTS (2002)
Bart Vermeulen, Steven Oostdijk, Frank Bouwman
digital video platform system chip. ITC (2001)
Bart Vermeulen, Gert-Jan van Rootselaar
Silicon debug of a co-processor array for video applications. HLDVT (2000)
Gert-Jan van Rootselaar, Bart Vermeulen
Silicon debug: scan chains alone are not enough. ITC (1999)