Sujan Pandey

Publication Activity (10 Years)

Years Active: 2005-2014
Publications (10 Years): 0

Top Topics

Delay Insensitive

Safety Critical

Top Venues

Publications

Sujan Pandey, Bart Vermeulen
Transient errors resiliency analysis technique for automotive safety critical applications. DATE (2014)
Sujan Pandey, Klaas Brink
Soft-errors resilient logic optimization for low power. IOLTS (2012)
Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner
Process variations aware robust on-chip bus architecture synthesis for MPSoCs. ISCAS (2008)
Sujan Pandey, Rolf Drechsler
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival. ASP-DAC (2008)
Sujan Pandey, Rolf Drechsler
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. DATE (2008)
Sujan Pandey, Christian Genz, Rolf Drechsler
Co-synthesis of custom on-chip bus and memory for MPSoC architectures. VLSI-SoC (2007)
Tudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner
On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. PATMOS (2007)
Sujan Pandey, Manfred Glesner
Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. IEEE Trans. Very Large Scale Integr. Syst. 15 (10) (2007)
Tudor Murgan, Oliver Mitea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. VLSI-SoC (2006)
Sujan Pandey, Manfred Glesner
Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique. ISCAS (2006)
Sujan Pandey, Nurten Utlu, Manfred Glesner
Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture. VLSI-SoC (2006)
Sujan Pandey, Manfred Glesner
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. DAC (2006)
Sujan Pandey, Tudor Murgan, Manfred Glesner
Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis. VLSI-SoC (2006)
Sujan Pandey, Manfred Glesner
Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture. FPL (2006)
Thomas Hollstein, Sujan Pandey, Manfred Glesner
Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip. ReCoSoC (2005)
Sujan Pandey, Manfred Glesner, Max Mühlhäuser
Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture. SBCCI (2005)
Sujan Pandey, Manfred Glesner, Max Mühlhäuser
On-Chip Communication Topology Synthesis for a Shared Memory Architecture. FPL (2005)
Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser
High level hardware/software communication estimation in shared memory architecture. ISCAS (1) (2005)