Soft-errors resilient logic optimization for low power.
Sujan PandeyKlaas BrinkPublished in: IOLTS (2012)
Keyphrases
- low power
- logic circuits
- power consumption
- high speed
- low cost
- delay insensitive
- high power
- single chip
- vlsi architecture
- digital signal processing
- low power consumption
- wireless transmission
- vlsi circuits
- image sensor
- cmos technology
- gate array
- computer simulation
- real time
- power reduction
- signal processor
- ultra low power