Jeff Rearick

Publication Activity (10 Years)

Years Active: 1993-2023
Publications (10 Years): 15

Top Topics

Issues And Trends

Bandwidth Utilization

Neural Architectures

Top Venues

Publications

Li-C. Wang, Jeff Rearick
Welcome Message ITC 2023. ITC (2023)
Michele Portolan, Martin Keim, Jeff Rearick, Heiko Ehrenberg
Refreshing the JTAG Family. VTS (2023)
Michael Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Songlin Zuo
IEEE P1687.1: Extending the Network Boundaries for Test. ITC (2022)
Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Michele Portolan, Martin Keim
Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling of Non-TAP Interfaces. ETS (2021)
Michele Portolan, Jeff Rearick, Martin Keim
Linking Chip, Board, and System Test via Standards. ETS (2020)
Hans Martin von Staudt, Mohamed Anas Benhebibi, Jeff Rearick, Michael Laisne
Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices. ITC (2020)
Mike Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, M. Abdalwahab, Bradford G. Van Treuren, Jeff Rearick
Modeling Novel Non-JTAG IEEE 1687-Like Architectures. ITC (2020)
Jeff Rearick, Alfred L. Crouch, Hans Martin von Staudt
Innovative Practices on IEEE 1687.xyz. VTS (2019)
Wim Dobbelaere, On Semi, Massimo Violante, Turin Polytechnic, Jeff Rearick
Innovative practices on quality levels of A/MS devices. VTS (2018)
Michael Alfano, Bryan Black, Jeff Rearick, Joseph Siegel, Michael Su, Julius Din
Unleashing Fury: A New Paradigm for 3-D Design and Test. IEEE Des. Test 34 (1) (2017)
Yan Dong, Grady Giles, GuoLiang Li, Jeff Rearick, John Schulze, James Wingfield, Tim Wood
Maximizing scan pin and bandwidth utilization with a scan routing fabric. ITC (2017)
Peter Sarson, Jeff Rearick
Use models for extending IEEE 1687 to analog test. ITC (2017)
Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick
Streaming Access to ADCs and DACs for Mixed-Signal ATPG. IEEE Des. Test 33 (6) (2016)
Yan Dong, Grady Giles, GuoLiang Li, Jeff Rearick, John Schulze, James Wingfield, Tim Wood
Toward more efficient scan data bandwidth utilization on modern SOCs. SoCC (2016)
Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick
Streaming fast access to ADCs and DACs for mixed-signal ATPG. ITC (2015)
Sankar Gurumurthy, Mustansir Pratapgarhwala, Curtis Gilgan, Jeff Rearick
Comparing the effectiveness of cache-resident tests against cycleaccurate deterministic functional patterns. ITC (2014)
Jeff Rearick
Magical thinking applied to test engineering reality (and vice versa). ETS (2013)
Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman, Krishnendu Chakrabarty, Erik Larsson
Re-using chip level DFT at board level. ETS (2012)
Baosheng Wang, Jayalakshmi Rajaraman, Kanwaldeep Sobti, Derrick Losli, Jeff Rearick
Structural tests of slave clock gating in low-power flip-flop. VTS (2011)
Vance Threatt, Atchyuth Gorti, Jeff Rearick, Shaishav Parikh, Anirudh Kadiyala, Aditya Jagirdar, Andy Halliday
Vendor-agnostic native compression engine. ITC (2010)
Janine Chen, Jing Zeng, Li-C. Wang, Jeff Rearick, Michael Mateja
Selecting the most relevant structural Fmax for system Fmax correlation. VTS (2010)
Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick
Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. IEEE Des. Test Comput. 26 (3) (2009)
Sankar Gurumurthy, D. Bertanzetti, P. Jakobsen, Jeff Rearick
Cache-resident self-testing for I/O circuitry. ITC (2009)
Ken Posse, Al Crouch, Jeff Rearick
IEEE P1687 IJTAG a presentation of current technology. ITC (2009)
Bart Vermeulen, Neal Stollon, Rolf Kühnis, Gary Swoboda, Jeff Rearick
Overview of Debug Standardization Activities. IEEE Des. Test Comput. 25 (3) (2008)
Jeff Rearick
This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company. ITC (2008)
Donghwi Lee, Erik H. Volkerink, Intaik Park, Jeff Rearick
Empirical Validation of Yield Recovery Using Idle-Cycle Insertion. IEEE Des. Test Comput. 24 (4) (2007)
Jeff Rearick
Embedded Test Features for High-Speed Serial I/O. CICC (2007)
Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick
Test cost reduction for the AMD™ Athlon processor using test partitioning. ITC (2007)
Ken Posse, Al Crouch, Jeff Rearick, Bill Eklow, Mike Laisne, Ben Bennetts, Jason Doege, Mike Ricchetti, Jean-Francois Cote
IEEE P1687: Toward Standardized Access of Embedded Instrumentation. ITC (2006)
Jeff Rearick, Aaron Volz
A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing. ITC (2006)
Jeff Rearick
A Survey of Test Problems and Solutions. ITC (2006)
Jeff Rearick, Bill Eklow, Ken Posse, Al Crouch, Ben Bennetts
IJTAG (internal JTAG): a step toward a DFT standard. ITC (2005)
Jeff Rearick, Richard Rodgers
Calibrating clock stretch during AC scan testing. ITC (2005)
Jeff Rearick, Sylvia Patterson, Krista Dorner
Integrating Boundary Scan into Multi-GHz I/O Circuitry. ITC (2004)
Suzette Vandivier, Mark Wahl, Jeff Rearick
First IC Validation of IEEE Std. 1149.6. ITC (2003)
Manish Sharma, Janak H. Patel, Jeff Rearick
Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. VTS (2003)
Young Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick
Frequency detection-based boundary-scan testing of AC coupled nets. ITC (2001)
Jeff Rearick
Too much delay fault coverage is a bad thing. ITC (2001)
Peter C. Maxwell, Jeff Rearick
Deception by design: fooling ourselves with gate-level models. ITC (2000)
Jeff Rearick
Practical scan test generation and application for embedded FIFOs. ITC (1999)
Jeff Rearick
Buying time for the stuck-at fault model. ITC (1998)
Peter C. Maxwell, Jeff Rearick
Estimation of defect-free IDDQ in submicron circuits using switch level simulation. ITC (1998)
Jeff Rearick
The Case of Partial Scan. ITC (1997)
Jeff Rearick, Janak H. Patel
Fast and Accurate CMOS Bridging Fault Simulation. ITC (1993)