Structural tests of slave clock gating in low-power flip-flop.

Baosheng Wang Jayalakshmi Rajaraman Kanwaldeep Sobti Derrick Losli Jeff Rearick

Published in: VTS (2011)

Keyphrases

power dissipation
low power
power consumption
flip flops
high speed
low cost
power reduction
cmos technology
logic circuits
digital signal processing
low power consumption
master slave
mixed signal
power saving
energy efficiency
frame rate
gate array
computer vision
design methodology
signal processing