Anuja Sehgal

Publication Activity (10 Years)

Years Active: 2003-2009
Publications (10 Years): 0

Publications

Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield
Test access mechanism for multiple identical cores. ITC (2009)
Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick
Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. IEEE Des. Test Comput. 26 (3) (2009)
Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty
Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. IEEE Trans. Computers 58 (3) (2009)
Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield
Test Access Mechanism for Multiple Identical Cores. ITC (2008)
Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Power-aware SoC test planning for effective utilization of port-scalable testers. ACM Trans. Design Autom. Electr. Syst. 13 (3) (2008)
Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores CoRR (2007)
Anuja Sehgal, Krishnendu Chakrabarty
Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs. IEEE Trans. Computers 56 (1) (2007)
Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick
Test cost reduction for the AMD™ Athlon processor using test partitioning. ITC (2007)
Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. DATE (2006)
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
Test infrastructure design for mixed-signal SOCs with wrapped analog cores. IEEE Trans. Very Large Scale Integr. Syst. 14 (3) (2006)
Anuja Sehgal, Krishnendu Chakrabarty
Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs. ICCAD (2005)
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs. ICCD (2005)
Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores. DATE (2005)
Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. ITC (2004)
Anuja Sehgal, Krishnendu Chakrabarty
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures. DATE (2004)
Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty
SOC test planning using virtual test access architectures. IEEE Trans. Very Large Scale Integr. Syst. 12 (12) (2004)
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers. ICCAD (2003)
Anuja Sehgal, Aishwarya Dubey, Erik Jan Marinissen, Clemens Wouters, Harald P. E. Vranken, Krishnendu Chakrabarty
Yield analysis for repairable embedded memories. ETW (2003)
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. DAC (2003)