Sudarshan Bahukudumbi

Publication Activity (10 Years)

Years Active: 2005-2009
Publications (10 Years): 0

Duke University, Durham, NC, USA (PHD)

Education History

Duke University, Durham, NC, USA

PHD

Publications

Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (1) (2009)
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In. IEEE Trans. Very Large Scale Integr. Syst. 17 (12) (2009)
Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar
Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs. IEEE Trans. Very Large Scale Integr. Syst. 17 (4) (2009)
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Power Management for Wafer-Level Test During Burn-In. ATS (2008)
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In. VTS (2008)
Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Power-aware SoC test planning for effective utilization of port-scalable testers. ACM Trans. Design Autom. Electr. Syst. 13 (3) (2008)
Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Richard Kacprowicz
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs. DATE (2008)
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs. VLSI Design (2007)
Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar
AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. ASP-DAC (2007)
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Wafer-Level Modular Testing of Core-Based SoCs. IEEE Trans. Very Large Scale Integr. Syst. 15 (10) (2007)
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs. ITC (2006)
Sudarshan Bahukudumbi, Krishna Bharath
A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores. VLSI Design (2005)

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Publication Activity (10 Years)

Sudarshan Bahukudumbi