Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs.
Sudarshan BahukudumbiKrishnendu ChakrabartyPublished in: VLSI Design (2007)
Keyphrases
- test cases
- test generation
- test data
- software testing
- test suite
- neural network
- usability testing
- optimization algorithm
- optimization method
- integrated circuit
- regression testing
- statistical tests
- global optimization
- higher level
- data sets
- fine tuning
- optimization problems
- testing process
- optimal selection
- levels of abstraction
- digital media
- information systems