A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores.

Sudarshan Bahukudumbi Krishna Bharath

Published in: VLSI Design (2005)

Keyphrases

low overhead
analog circuits
high speed
load balancing
high reliability
digital circuits
fault diagnosis
neural network
low power
communication cost
energy efficient
real time
parallel algorithm
shared memory
design methodology
distributed breakout