Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs.
Sudarshan BahukudumbiKrishnendu ChakrabartyPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2009)
Keyphrases
- test cases
- software testing
- test generation
- test data
- test sequences
- structural equation modeling
- global optimization
- optimization problems
- testing process
- statistical tests
- test case generation
- higher level
- optimization algorithm
- test suite
- test data generation
- regression testing
- model based testing
- statistical significance
- optimization process
- massively parallel
- lower level
- constrained optimization
- optimization methods
- optimization method
- genetic algorithm