Mauro Olivieri

ORCID

Publication Activity (10 Years)

Years Active: 1992-2024
Publications (10 Years): 40

Top Venues

ApplePies

PRIME

CoRR

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Mauro Olivieri
Exploring Variable Latency Dividers in Vector Hardware Accelerators. PRIME (2024)
Marcello Barbirotta, Francesco Menichelli, Abdallah Cheikh, Antonio Mastrandrea, Marco Angioli, Mauro Olivieri
Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems. IEEE Access 12 (2024)
Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme. IEEE Trans. Computers 73 (7) (2024)
Saeid Jamili, Antonio Mastrandrea, Abdallah Cheikh, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach. ApplePies (2023)
Mate Kovac, Leon Dragic, Branimir Malnar, Francesco Minervini, Oscar Palomar, Carlos Rojas, Mauro Olivieri, Josip Knezovic, Mario Kovac
FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit. Microprocess. Microsystems 97 (2023)
Marcello Barbirotta, Francesco Menichelli, Antonio Mastrandrea, Abdallah Cheikh, Marco Angioli, Saeid Jamili, Mauro Olivieri
Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects. ApplePies (2023)
Francesco Bellotti, Elisa Bricco, Agostino G. Bruzzone, Daniele D. Caviglia, Ermanno Di Zitti, Paolo Gastaldo, Daniele Grosso, Lauro Magnani, Mauro Olivieri, Marco Raggio, Maurizio Valle, Alessandro Verri, Riccardo Berta
Alessandro De Gloria, a Pioneer in Electronic Engineering Applications. ApplePies (2023)
Francesco Minervini, Oscar Palomar, Osman S. Unsal, Enrico Reggiani, Josue V. Quiroga, Joan Marimon, Carlos Rojas, Roger Figueras, Abraham Ruiz, Alberto González, Jonnatan Mendoza, Iván Vargas, César Hernández, Joan Cabre, Lina Khoirunisya, Mustapha Bouhali, Julian Pavon, Francesc Moll, Mauro Olivieri, Mario Kovac, Mate Kovac, Leon Dragic, Mateo Valero, Adrián Cristal
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications. ACM Trans. Archit. Code Optim. 20 (2) (2023)
Marco Angioli, Marcello Barbirotta, Antonio Mastrandrea, Saeid Jamili, Mauro Olivieri
Automatic Hardware Accelerators Reconfiguration through LinearUCB Algorithms on a RISC-V Processor. PRIME (2023)
Enrico Reggiani, Alessandro Pappalardo, Max Doblas, Miquel Moretó, Mauro Olivieri, Osman Sabri Unsal, Adrián Cristal
Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices. HPCA (2023)
Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Saeid Jamili, Francesco Menichelli, Mauro Olivieri
Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design. ApplePies (2023)
Enrico Reggiani, Cristóbal Ramírez Lazo, Roger Figueras Bagué, Adrián Cristal, Mauro Olivieri, Osman Sabri Unsal
BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge. ASPLOS (2022)
Saeid Jamili, Abdallah Cheikh, Antonio Mastrandrea, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. ApplePies (2022)
Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration. PRIME (2022)
Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors. IEEE Access 10 (2022)
Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators. ApplePies (2022)
Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. DFT (2021)
Marco Aldinucci, Giovanni Agosta, Antonio Andreini, Claudio Agostino Ardagna, Andrea Bartolini, Alessandro Cilardo, Biagio Cosenza, Marco Danelutto, Roberto Esposito, William Fornaciari, Roberto Giorgi, Davide Lengani, Raffaele Montella, Mauro Olivieri, Sergio Saponara, Daniele Simoni, Massimo Torquati
The Italian research on HPC key technologies across EuroHPC. CF (2021)
Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores. IEEE Micro 41 (2) (2021)
Davide Bellizia, Simone Bongiovanni, Mauro Olivieri, Giuseppe Scotti
SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2020)
Marcello Barbirotta, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Luigi Blasi, Abdallah Cheikh, Stefano Sordillo, Fabio Di Gennaro, Mauro Olivieri
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment. DFT (2020)
Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores. CoRR (2020)
Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor. ApplePies (2019)
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
Quality Aware Selective ECC for Approximate DRAM. ApplePies (2019)
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
Full System Emulation of Approximate Memory Platforms with AppropinQuo. J. Low Power Electron. 15 (1) (2019)
Fabrizio Gagliardi, Miquel Moretó, Mauro Olivieri, Mateo Valero
The international race towards Exascale in Europe. CCF Trans. High Perform. Comput. 1 (1) (2019)
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
Quality Aware Approximate Memory in RISC-V Linux Kernel. PRIME (2019)
Luigi Blasi, Francesco Vigli, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. ApplePies (2019)
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
Approximate Memory Support for Linux Early Allocators in ARM Architectures. ApplePies (2018)
Giulia Stazi, Federica Silvestri, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing. ApplePies (2018)
Zia Abbas, Andleeb Zahra, Mauro Olivieri
LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits. VDAT (2018)
Giulia Stazi, Lorenzo Adani, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder. ISC Workshops (2018)
Mauro Olivieri, Usman Khalid, Antonio Mastrandrea, Francesco Menichelli
Characterizing noise pulse effects on the power consumption of idle digital cells. ISCAS (2018)
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space. NGCAS (2018)
Usman Khalid, Antonio Mastrandrea, Mauro Olivieri
Effect of NBTI/PBTI Aging and Process Variations on Write Failures in MOSFET and FinFET Flip-Flops. CoRR (2017)
Mauro Olivieri, Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli
Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores. NGCAS (2017)
Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes. CoRR (2017)
Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes. ApplePies (2017)
Francesco Menichelli, Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri
An Emulator for Approximate Memory Platforms Based on QEmu. ApplePies (2016)
Zia Abbas, Mauro Olivieri
Optimal transistor sizing for maximum yield in variation-aware standard cell design. Int. J. Circuit Theory Appl. 44 (7) (2016)
Claudio Santo Malavenda, Francesco Menichelli, Mauro Olivieri
Narrowband Delay Tolerant Protocols for WSN Applications: Characterization and Selection Guide. ApplePies (2015)
Usman Khalid, Antonio Mastrandrea, Mauro Olivieri
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops. Microelectron. Reliab. 55 (12) (2015)
Luca Benini, Renu Mehra, Mauro Olivieri
Message from the general chairs. ISLPED (2015)
Usman Khalid, Antonio Mastrandrea, Mauro Olivieri
Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops. DSD (2014)
Mauro Olivieri, Antonio Mastrandrea
Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Francesco Menichelli, Mauro Olivieri
A Platform-Based Emulator for Mass-Storage Flash Cards Evaluation in Embedded Systems. ApplePies (2014)
Marco Marazza, Francesco Menichelli, Mauro Olivieri, Orlando Ferrante, Alberto Ferrari
A Model-Based Methodology to Generate Code for Timer Units. ApplePies (2014)
Zia Abbas, Antonio Mastrandrea, Mauro Olivieri
A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs. IEEE Trans. Very Large Scale Integr. Syst. 22 (12) (2014)
Claudio Santo Malavenda, Francesco Menichelli, Mauro Olivieri
A Regulation-Based Security Evaluation Method for Data Link in Wireless Sensor Network. J. Comput. Networks Commun. 2014 (2014)
Zia Abbas, Mauro Olivieri
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells. Microelectron. J. 45 (2) (2014)
Fabrizio Ramundo, Paolo Nenzi, Mauro Olivieri
First integration of MOSFET band-to-band-tunneling current in BSIM4. Microelectron. J. 44 (1) (2013)
Claudio Santo Malavenda, Francesco Menichelli, Mauro Olivieri
Wireless and Ad Hoc Sensor Networks: An Industrial Example Using Delay Tolerant, Low Power Protocols for Security-Critical Applications. ApplePies (2013)
Simone Bongiovanni, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family. MIXDES (2013)
Mauro Olivieri, Antonio Mastrandrea
A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures. VLSI Design 2013 (2013)
Zia Abbas, Mauro Olivieri, Marat Yakupov, Andreas Ripp
Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+). Microelectron. J. 44 (4) (2013)
Claudio Santo Malavenda, Francesco Menichelli, Mauro Olivieri
Delay-Tolerant, Low-Power Protocols for Large Security-Critical Wireless Sensor Networks. J. Comput. Networks Commun. 2012 (2012)
Zia Abbas, Marat Yakupov, Mauro Olivieri, Andreas Ripp, Gunter Strube
Yield optimization for low power current controlled current conveyor. SBCCI (2012)
Francesco Menichelli, Mauro Olivieri, Simone Smorfa
Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores. ISCAS (2011)
Francesco Menichelli, Mauro Olivieri
TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction. Wirel. Sens. Netw. 2 (11) (2010)
Francesco Menichelli, Mauro Olivieri
Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips. IEEE Trans. Very Large Scale Integr. Syst. 17 (2) (2009)
Francesco Paterna, Luca Benini, Andrea Acquaviva, Francesco Papariello, Giuseppe Desoli, Mauro Olivieri
Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip. DATE (2009)
Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Alessandro Trifiletti
High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips. IEEE Trans. Dependable Secur. Comput. 5 (3) (2008)
Luca Giancane, Piero Marietti, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
A new dynamic differential logic style as a countermeasure to power analysis attacks. ICECS (2008)
Roberto Mancuso, Simone Smorfa, Mauro Olivieri
A novel high-quality YUV-based image coding technique for efficient image storage in portable electronic appliances. IEEE Trans. Consumer Electron. 54 (2) (2008)
Marco Bucci, Raimondo Luzzi, Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Alessandro Trifiletti
Testing power-analysis attack susceptibility in register-transfer level designs. IET Inf. Secur. 1 (3) (2007)
Mauro Olivieri, Roberto Mancuso, Friedbert Riedel
A Reconfigurable, Low Power, Temperature Compensated IC for 8-segment Gamma Correction Curve in TFT, OLED and PDP Displays. IEEE Trans. Consumer Electron. 53 (2) (2007)
Mauro Olivieri, Francesco Pappalardo, Simone Smorfa, Giuseppe Visalli
Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units. IEEE Trans. Circuits Syst. II Express Briefs (8) (2007)
Simone Smorfa, Mauro Olivieri
HW-SW optimisation of JPEG2000 wavelet transform for dedicated multimedia processor architectures. IET Comput. Digit. Tech. 1 (2) (2007)
Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. PATMOS (2007)
Manfred Josef Aigner, Stefan Mangard, Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Thomas Popp, Giuseppe Scotti, Alessandro Trifiletti
Side channel analysis resistant design flow. ISCAS (2006)
Simone Smorfa, Mauro Olivieri, Roberto Mancuso, Martin Lienhard
A physical-level LCD driver model and simulator with application to pixel crosstalk suppression. IEEE Trans. Consumer Electron. 52 (3) (2006)
Luca Benini, Davide Bertozzi, Alessandro Bogliolo, Francesco Menichelli, Mauro Olivieri
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC. J. VLSI Signal Process. 41 (2) (2005)
Francesco Menichelli, Mauro Olivieri, Simone Smorfa, Irene Zaccardini
Software optimization of the JPEG2000 algorithm on a VLIW CPU core for system-on-chip implementation. Circuits, Signals, and Systems (2005)
Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
Design issues for bus switch systems in deep sub-micro metric CMOS technologies. Circuits, Signals, and Systems (2005)
Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control. IEEE Trans. Very Large Scale Integr. Syst. 13 (5) (2005)
Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
statistical analysis, for reducing the energy dissipation in a bus-switch encoder. Circuits, Signals, and Systems (2005)
Mauro Olivieri, Simone Smorfa, Alessandro Trifiletti
Design and Test of a Novel Programmable Clock Generator Semi-Custom Core for Energy-Efficient Systems-on-Chips. J. Low Power Electron. 1 (3) (2005)
Manfred Josef Aigner, Stefan Mangard, Renato Menicocci, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
A novel CMOS logic style with data independent power consumption. ISCAS (2) (2005)
Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
Encoding circuits for low power optical on-chip communications. ISCAS (5) (2005)
Mauro Olivieri, Mirko Scarana, Simone Smorfa
Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique. ISCAS (5) (2005)
Mauro Olivieri, Mirko Scarana, Giuseppe Scotti, Alessandro Trifiletti
Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques. PATMOS (2004)
Luca Benini, Francesco Menichelli, Mauro Olivieri
A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems. IEEE Trans. Computers 53 (4) (2004)
Francesco Centurelli, Stefano Costi, Mauro Olivieri, Salvatore Pennisi, Alessandro Trifiletti
Robust three-state PFD architecture with enhanced frequency acquisition capabilities. ISCAS (4) (2004)
Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
Bus-switch coding for reducing power dissipation in off-chip buses. IEEE Trans. Very Large Scale Integr. Syst. 12 (12) (2004)
Federico Angiolini, Francesco Menichelli, Alberto Ferrero, Luca Benini, Mauro Olivieri
A post-compiler approach to scratchpad mapping of code. CASES (2004)
Francesco Menichelli, Mauro Olivieri, Luca Benini, Monica Donno, Labros Bisdounis
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design. DATE (2004)
Mauro Olivieri, Marco Raspa
Power Efficiency of Application-Dependent Self-Configuring Pipeline Depth in DSP Microprocessors. IPDPS (2003)
Mauro Olivieri
Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design. IEEE Trans. Very Large Scale Integr. Syst. 10 (5) (2002)
Mauro Olivieri
Correction to "design of synchronous and asynchronous variable-latency pipelined multipliers". IEEE Trans. Very Large Scale Integr. Syst. 9 (4) (2001)
Mauro Olivieri, Alessandro Trifiletti
An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores. ISCAS (4) (2001)
Mauro Olivieri
A genetic approach to the design space exploration of superscalar microprocessor architectures. ISCAS (5) (2001)
Mauro Olivieri
Design of synchronous and asynchronous variable-latency pipelined multipliers. IEEE Trans. Very Large Scale Integr. Syst. 9 (2) (2001)
Alessandro De Gloria, Mauro Olivieri
An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors. ISCAS (4) (2001)
Mauro Bertacchi, Alessandro De Gloria, Daniele Grosso, Mauro Olivieri
Semicustom Design of an IEEE 1394-Compliant Reusable IC Core. IEEE Des. Test Comput. 17 (3) (2000)
Alessandro De Gloria, Paolo Palma, Mauro Olivieri
Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power Applications. EUROMICRO (1999)
Mauro Olivieri, Alessandro Trifiletti, Alessandro De Gloria
A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications. ICCD (1999)
Alessandra Costa, Alessandro De Gloria, Fabrizio Giudici, Mauro Olivieri
Fuzzy logic microcontroller. IEEE Micro 17 (1) (1997)
Alessandro De Gloria, Mauro Olivieri
An asynchronous distributed architecture model for the Boltzmann machine control mechanism. IEEE Trans. Neural Networks 7 (6) (1996)
Alessandro De Gloria, Mauro Olivieri
Statistical Carry Lookahead Adders. IEEE Trans. Computers 45 (3) (1996)
Alessandra Costa, Alessandro De Gloria, Mauro Olivieri
Hardware design of asynchronous fuzzy controllers. IEEE Trans. Fuzzy Syst. 4 (3) (1996)

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Publication Activity (10 Years)

Top Topics

Top Venues

Mauro Olivieri