Francesco Centurelli

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 45

Top Topics

Design Guidelines

Building Blocks

Top Venues

Int. J. Circuit Theory Appl.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Riccardo Della Sala, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti
On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation. IEEE Access 12 (2024)
Riccardo Della Sala, Cristian Bocciarelli, Valerio Spinogatti, Francesco Centurelli, Alessandro Trifiletti
Enhancing Performance of Ultra-Low Voltage Body-Driven Comparators Through Clocked Supply Voltage. PRIME (2024)
Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti
A Novel Technique to Design Ultra-Low Voltage and Ultra-Low Power Inverter-Based OTAs. PRIME (2024)
Valerio Spinogatti, Cristian Bocciarelli, Lorenzo Eusebio, Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
A 150 MS/s, 10 bit SAR ADC Featuring a Modified Quasi-Monotonic Switching Scheme. PRIME (2024)
Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo
Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications. IEEE Access 12 (2024)
Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti
A Novel High Performance Standard-Cell Based ULV OTA Exploiting an Improved Basic Amplifier. IEEE Access 12 (2024)
Riccardo Della Sala, Cristian Bocciarelli, Francesco Centurelli, Valerio Spinogatti, Alessandro Trifiletti
A Novel Ultra-Low Voltage Fully Synthesizable Comparator exploiting NAND Gates. PRIME (2023)
Riccardo Della Sala, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations. IEEE Access 11 (2023)
Cristian Bocciarelli, Francesco Centurelli, Pietro Monsurrò, Valerio Spinogatti, Alessandro Trifiletti
A 17 GHz inductorless low-pass filter based on a quasi-Sallen-Key approach. Int. J. Circuit Theory Appl. 51 (11) (2023)
Alessandro Fava, Francesco Centurelli, Andrea Vittimberga, Giuseppe Scotti
Wide-Band Shared LNA for Large Scale Neural Recording Applications. SMACD (2023)
Alessandro Fava, Francesco Centurelli, Giuseppe Scotti
A Detailed Model of Cyclostationary Noise in Switched-Resistor Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (2) (2023)
Francesco Centurelli, Pietro Monsurrò, Pasquale Tommasino, Alessandro Trifiletti
A Novel Parallel Digitizer With a Pulseless Mixing-Filtering-Processing Architecture and Its Implementation in a SiGe HBT Technology at 40GS/s. IEEE Access 11 (2023)
Gianluca Barile, Vincenzo Stornelli, Leonardo Pantoli, Davide Colaiuda, Francesco Centurelli, Pasquale Tommasino, Alessandro Trifiletti, Giuseppe Ferri
CMOS Adaptive Biased Second Generation Voltage Conveyor. BATS (2023)
Cristian Bocciarelli, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Valerio Spinogatti, Pasquale Tommasino, Alessandro Trifiletti
High-Accuracy Low-Cost Generalized Complex Pruned Volterra Models for Nonlinear Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (9) (2023)
Riccardo Della Sala, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
A body-driven rail-to-rail 0.3 V operational transconductance amplifier exploiting current gain stages. Int. J. Circuit Theory Appl. 51 (5) (2023)
Valerio Spinogatti, Cristian Bocciarelli, Francesco Centurelli, Riccardo Della Sala, Alessandro Trifiletti
Robust Body Biasing Techniques for Dynamic Comparators. PRIME (2023)
Cristian Bocciarelli, Francesco Centurelli, Riccardo Della Sala, Valerio Spinogatti, Alessandro Trifiletti
A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing. PRIME (2023)
Valerio Spinogatti, Riccardo Della Sala, Cristian Bocciarelli, Francesco Centurelli, Alessandro Trifiletti
An Improved Strong Arm Comparator With Integrated Static Preamplifier. IEEE Access 11 (2023)
Francesco Centurelli, Gianluca Giustolisi, Salvatore Pennisi, Giuseppe Scotti
A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs. IEEE Access 10 (2022)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti, Mauro D'Arco, Leopoldo Angrisani
General Approach to the Calibration of Innovative MFP Multichannel Digitizers. IEEE Trans. Instrum. Meas. 71 (2022)
Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti
A SiGe HBT 6th-Order 10 GHz Inductor-Less Anti-Aliasing Low-Pass Filter for High-Speed ATI Digitizers. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti
A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs. IEEE Access 10 (2022)
Riccardo Della Sala, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti
Sub-μW Front-End Low Noise Amplifier for Neural Recording Applications. PRIME (2022)
Riccardo Della Sala, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti
High-efficiency 0.3V OTA in CMOS 130nm technology using current mirrors with gain. PRIME (2022)
Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti
Enabling ULV Fully Synthesizable Analog Circuits: The BA Cell, a Standard-Cell-Based Building Block for Analog Design. IEEE Trans. Circuits Syst. II Express Briefs 69 (12) (2022)
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (2) (2021)
Francesco Centurelli, Alessandro Fava, Giuseppe Scotti, Alessandro Trifiletti
A Detailed Model of the Switched-Resistor Technique. IEEE Open J. Circuits Syst. 2 (2021)
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML. ISCAS (2021)
Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 29 (5) (2021)
Giandomenico Amendola, Luigi Boccia, Francesco Centurelli, Pascal Chevalier, Alessandro Fonte, Carmine Mustacchio, Andrea Pallotta, Pasquale Tommasino, Antonio Traversa, Alessandro Trifiletti
Compact E-Band I/Q Receiver in SiGe BiCMOS for 5G Backhauling Applications. IEEE Trans. Circuits Syst. II Express Briefs 68 (9) (2021)
Danilo Cellucci, Francesco Centurelli, Valerio Di Stefano, Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
0.6-V CMOS cascode OTA with complementary gate-driven gain-boosting and forward body bias. Int. J. Circuit Theory Appl. 48 (1) (2020)
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
Delay models and design guidelines for MCML gates with resistor or PMOS load. Microelectron. J. 99 (2020)
Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti
An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response. Int. J. Circuit Theory Appl. 48 (11) (2020)
Francesco Centurelli, Pietro Monsurrò, Vincenzo Stornelli, Gianluca Barile, Alessandro Trifiletti
Low-power class-AB 4th-order low-pass filter based on current conveyors with dynamic mismatch compensation of biasing errors. Int. J. Circuit Theory Appl. 48 (4) (2020)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
A low-power class-AB Gm-C biquad stage in CMOS 40nm technology. ICECS (2019)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
High-gain, high-CMRR class AB operational transconductance amplifier based on the flipped voltage follower. Int. J. Circuit Theory Appl. 47 (4) (2019)
Francesco Centurelli, Pietro Monsurrò, Gaetano Parisi, Pasquale Tommasino, Alessandro Trifiletti
A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR. IEEE Trans. Circuits Syst. II Express Briefs (11) (2018)
Francesco Centurelli, Pietro Monsurrò, Gaetano Parisi, Pasquale Tommasino, Alessandro Trifiletti
A fully-differential class-AB OTA with CMRR improved by local feedback. ECCTD (2017)
Francesco Centurelli, Pietro Monsurrò, Pasquale Tommasino, Alessandro Trifiletti
On the use of voltage conveyors for the synthesis of biquad filters and arbitrary networks. ECCTD (2017)
Francesco Centurelli, Pietro Monsurrò, Gaetano Parisi, Pasquale Tommasino, Alessandro Trifiletti
Fully Differential Class-AB OTA with Improved CMRR. J. Circuits Syst. Comput. 26 (11) (2017)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti, Gianluca Barile, Giuseppe Ferri, Leonardo Pantoli, Vincenzo Stornelli
Class-AB current conveyors based on the FVF. ECCTD (2017)
Gianluca Barile, L. Liberati, Giuseppe Ferri, Leonardo Pantoli, Vincenzo Stornelli, Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
Power-efficient dynamic-biased CCII. ECCTD (2017)
Francesco Centurelli, Pietro Monsurrò, Danilo Ruscio, Alessandro Trifiletti
A new class-AB Flipped Voltage Follower using a common-gate auxiliary amplifier. MIXDES (2016)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption. Int. J. Circuit Theory Appl. 44 (5) (2016)
Simone Bongiovanni, Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks. J. Cryptogr. Eng. 5 (4) (2015)
Francesco Centurelli, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti, Milena Djukanovic
Design of broad-band power amplifiers by means of an impedance transforming lossy equalizer. MIXDES (2014)
Francesco Centurelli, Roberto Antonio Gualano, Alessandro Trifiletti
A wideband amplifier topology based on positive capacitive feedback. Microelectron. J. 45 (1) (2014)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
Improved Digital Background Calibration of Time-Interleaved Pipeline A/D Converters. IEEE Trans. Circuits Syst. II Express Briefs (2) (2013)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2012)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
A class-AB very low voltage amplifier and sample & hold circuit. ECCTD (2011)
Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
A very low-voltage differential amplifier for opamp design. ECCTD (2011)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
A class-AB flipped voltage follower output stage. ECCTD (2011)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
An MDAC architecture with low sensitivity to finite opamp gain. ECCTD (2011)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
Behavioral Modeling for Calibration of Pipeline Analog-To-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2010)
Francesco Centurelli, Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies. IEEE Trans. Circuits Syst. II Express Briefs (6) (2009)
Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
A gain-enhancing technique for very low-voltage amplifiers. ISCAS (2008)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
A Simple Technique for Fast Digital Background Calibration of A/D Converters. EURASIP J. Adv. Signal Process. 2008 (2008)
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2007)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
A distortion model for pipeline Analog-to-Digital converters. ISCAS (2007)
Francesco Centurelli, Andrea Simonetti, Alessandro Trifiletti
A Sample-and-Hold Circuit with Very Low Gain Error for Time Interleaving Applications. ECCTD (2007)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
Power-constrained Bandwidth Optimization in Cascaded Open-loop Amplifiers. ECCTD (2007)
Francesco Centurelli, Alfio Dario Grasso, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
CMOS High-CMRR Current Output Stages. IEEE Trans. Circuits Syst. II Express Briefs (9) (2007)
Alfio Dario Grasso, Salvatore Pennisi, Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
CMOS Miller OTA with Body-Biased Output Stage. ECCTD (2007)
Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. PATMOS (2007)
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
A model for the distortion due to switch on-resistance in sample-and-hold circuits. ISCAS (2006)
Marco Balsi, Francesco Centurelli, Piero Marietti, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti, Giancarlo Valente
Validation of a statistical non-linear model of GaAs HEMT MMIC's by hypothesis testing and principal components analysis. ISCAS (2006)
Alberto Maria Bersani, Francesco Centurelli, Luca Fontana, Alessandro Trifiletti
Analytic transient solution of SCFL logic gates. Int. J. Circuit Theory Appl. 33 (5) (2005)
Francesco Centurelli, G. Lulli, Piero Marietti, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
High-speed CMOS-to-ECL pad driver in 0.18µm CMOS. ISCAS (1) (2005)
Francesco Centurelli, Alessandro Golfarelli, Jesus Guinea, Leonardo Masini, Damiana Morigi, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti
A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability. IEEE Trans. Very Large Scale Integr. Syst. 13 (2) (2005)
Francesco Centurelli, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti
A high-speed low-voltage phase detector for clock recovery from NRZ data. ISCAS (4) (2004)
Francesco Centurelli, Stefano Costi, Mauro Olivieri, Salvatore Pennisi, Alessandro Trifiletti
Robust three-state PFD architecture with enhanced frequency acquisition capabilities. ISCAS (4) (2004)
Marco Balsi, Francesco Centurelli, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti
An accurate behavioral model of phase detectors for clock recovery circuits. ISCAS (4) (2003)
Francesco Centurelli, Salvatore Pennisi, Alessandro Trifiletti
Current output stage with improved CMRR. ICECS (2003)
Marco Balsi, Francesco Centurelli, Salvatore Pennisi, Alessandro Trifiletti
A tree-like amplifier architecture for large gain-bandwidth product. ICECS (2002)
Marco Balsi, Francesco Centurelli, Salvatore Pennisi, Alessandro Trifiletti
Bipolar differential cell with improved bandwidth performance. ICECS (2002)
Andrea Pallotta, Francesco Centurelli, Alessandro Trifiletti
A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers. ISLPED (2000)
Andrea Pallotta, Francesco Centurelli, Francesco Loriga, Alessandro Trifiletti
A monolithic 2.5-Gb/s clock and data recovery circuit based on Silicon bipolar technology. SYBEN (1998)