Gaetano Palumbo

ORCID

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 55

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

ICECS

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Access

Publications

Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo
Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications. IEEE Access 12 (2024)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
An Energy-Efficient Design Strategy for Dickson Charge Pumps with Linear Distributed Capacitance. NEWCAS (2023)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
Fully On-Chip Charge Pump-based Boost Converter in 65-nm CMOS for Single Solar Cell Powered IC. ISCAS (2023)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
Triple Clock Boosted Voltage Multiplier: A Design Strategy to Heavily Reduce Rise Time. NEWCAS (2023)
Javier Beloso-Legarra, Antonio Lopez-Martin, Carlos Aristoteles De la Cruz, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
GBW Optimization in Two-Stage OTAs Operating in Weak Inversion. DCIS (2023)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
Very-Low-Voltage Charge Pump Topologies for IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (6) (2023)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa
A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers. IEEE Access 10 (2022)
Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo, Giuseppe Scotti
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers. IEEE Access 10 (2022)
Federico Nicolas Guerrero, Enrique Mario Spinelli, Alfio Dario Grasso, Gaetano Palumbo
Double-Differential Amplifier for sEMG Measurement by Means of a Current-Mode Approach. IEEE Access 10 (2022)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
The Dickson Charge Pump as a Signal Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (9) (2022)
Gianluca Giustolisi, Gaetano Palumbo
Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders. IEEE Access 10 (2022)
Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi
Single miller capacitor frequency compensation techniques: Theoretical comparison and critical review. Int. J. Circuit Theory Appl. 50 (5) (2022)
Hamed Aminzadeh, Alfio Dario Grasso, Gaetano Palumbo
A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers. IEEE Access 10 (2022)
Javier Beloso-Legarra, Alfio Dario Grasso, Antonio J. López-Martín, Gaetano Palumbo, Salvatore Pennisi
Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio. IEEE Trans. Circuits Syst. II Express Briefs 69 (7) (2022)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
A Bulk Current Regulation Technique for Dual-Branch Cross-Coupled Charge Pumps. IEEE Trans. Circuits Syst. II Express Briefs 69 (10) (2022)
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (2) (2021)
Gianluca Giustolisi, Gaetano Palumbo
Design of CMOS three-stage amplifiers for near-to-minimum settling-time. Microelectron. J. 107 (2021)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
Dickson Charge Pump: Design Strategy for Optimum Efficiency. NEWCAS (2021)
Gianluca Giustolisi, Gaetano Palumbo
Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (3) (2021)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa
Charge Pumps for Ultra-Low-Power Applications: Analysis, Design, and New Solutions. IEEE Trans. Circuits Syst. II Express Briefs 68 (8) (2021)
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML. ISCAS (2021)
Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 29 (5) (2021)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
Comparison of the Wide-Frequency Range Dynamic Behavior of the Dickson and Cockcroft-Walton Voltage Multipliers. MWSCAS (2021)
Gianluca Giustolisi, Gaetano Palumbo
Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints. ISCAS (2021)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes. IEEE Access 9 (2021)
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
Delay models and design guidelines for MCML gates with resistor or PMOS load. Microelectron. J. 99 (2020)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
A Subthreshold Cross-Coupled Hybrid Charge Pump for 50-mV Cold-Start. IEEE Access 8 (2020)
Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering. IEEE Trans. Circuits Syst. II Express Briefs (3) (2020)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
A High-Performance Charge Pump Topology for Very-Low-Voltage Applications. IEEE Trans. Circuits Syst. II Express Briefs (7) (2020)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
Charge Pump Improvement for Energy Harvesting Applications by Node Pre-Charging. IEEE Trans. Circuits Syst. (12) (2020)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
A simple and effective design strategy to increase power conversion efficiency of linear charge pumps. Int. J. Circuit Theory Appl. 48 (2) (2020)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo
Current-mode body-biased switch to increase performance of linear charge pumps. Int. J. Circuit Theory Appl. 48 (11) (2020)
Gaetano Palumbo, Giuseppe Scotti
A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS. IEEE Trans. Circuits Syst. (12) (2020)
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa
Linear distribution of capacitance in Dickson charge pumps to reduce rise time. Int. J. Circuit Theory Appl. 48 (4) (2020)
Gianluca Giustolisi, Gaetano Palumbo
In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2019)
Andrea Ballo, Alfio Dario Grasso, Gianluca Giustolisi, Gaetano Palumbo
Optimized Charge Pump With Clock Booster for Reduced Rise Time or Silicon Area. IEEE Trans. Circuits Syst. II Express Briefs (12) (2019)
Gianluca Giustolisi, Gaetano Palumbo, Salvatore Pennisi
Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies. Microelectron. J. 92 (2019)
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
Switched-Capacitor Power Management Integrated Circuit for Autonomous Internet of Things Node. IEEE Trans. Circuits Syst. II Express Briefs (10) (2018)
Andrea Ballo, Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo
A Clock Boosted Charge Pump with Reduced Rise Time. ICECS (2018)
Gianluca Giustolisi, Gaetano Palumbo
Bessel-like compensation of three-stage operational transconductance amplifiers. Int. J. Circuit Theory Appl. 46 (4) (2018)
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
Dual Push-Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays. IEEE Trans. Circuits Syst. II Express Briefs (12) (2018)
Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering. ICECS (2018)
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi, Davide Marano
Three-stage single-miller CMOS OTA driving 10 nF with 1.46-MHz GBW. ICICDT (2018)
Davide Bellizia, Gaetano Palumbo, Giuseppe Scotti, Alessandro Trifiletti
A Novel Very Low Voltage Topology to implement MCML XOR Gates. PRIME (2018)
Gianluca Giustolisi, Gaetano Palumbo
Design of CMOS OTAs with Settling-Time Constraints. ICECS (2018)
Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi
. IEEE Trans. Circuits Syst. II Express Briefs (11) (2018)
Gianluca Giustolisi, Gaetano Palumbo
Settling-time oriented OTA design through the approximation of the ideal delay. ISCAS (2018)
Gianluca Giustolisi, Gaetano Palumbo
Non-Inverting Class-AB CMOS Output Stage for Driving High-Capacitive Loads. ISCAS (2018)
Giulia Di Capua, Nuno Horta, Francisco V. Fernández, Günhan Dündar, Salvatore Pennisi, Gaetano Palumbo, Massimo Alioto, Gianluca Giustolisi
Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017. Integr. 63 (2018)
Gianluca Giustolisi, Gaetano Palumbo
Robust design of CMOS amplifiers oriented to settling-time specification. Int. J. Circuit Theory Appl. 45 (10) (2017)
Giuseppe Scotti, Davide Bellizia, Alessandro Trifiletti, Gaetano Palumbo
Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi, Willy Sansen
The noise performance of CMOS Miller operational transconductance amplifiers with embedded current-buffer frequency compensation. Int. J. Circuit Theory Appl. 45 (4) (2017)
Davide Marano, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
50-mW three-stage amplifier driving 10-nF with 2.7-MHz GBW. ICECS (2016)
Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro, Alfio Pappalardo
Verilog-a modeling of Silicon Photo-Multipliers. ISCAS (2016)
Davide Marano, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2016)
Massimo Alioto, Gaetano Palumbo, Elio Consoli
PVT variations in differential flip-flops: A comparative analysis. ECCTD (2015)
Massimo Alioto, Elio Consoli, Gaetano Palumbo
Comparative analysis of the robustness of master-slave flip-flops against variations. ICECS (2015)
Massimo Alioto, Elio Consoli, Gaetano Palumbo
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2015)
Gianluca Giustolisi, Gaetano Palumbo
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2015)
Davide Marano, Giovanni Bonanno, S. Garozzo, Giuseppe Romeo, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
A new enhanced PSPICE implementation of the equivalent circuit model of SiPM detectors. NEWCAS (2015)
Giuseppe Di Cataldo, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
Single-miller all-passive compensation network for three-stage OTAs. ECCTD (2015)
Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi
195-nW 120-dB subthreshold CMOS OTA driving up to 200 pF and occupying only 4.4-10-3 mm2. ICECS (2015)
Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo
Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes. IEEE Trans. Instrum. Meas. 64 (1) (2015)
Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi
Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2015)
Massimo Alioto, Elio Consoli, Gaetano Palumbo
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2015)
Massimo Alioto, Gaetano Palumbo, Elio Consoli
Variability budgetin pulsed flip-flops. NEWCAS (2015)
Alfio Dario Grasso, Davide Marano, Fermin Esparza-Alfaro, Antonio J. López-Martín, Gaetano Palumbo, Salvatore Pennisi
Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2014)
Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo
Monolithic quenching-and-reset circuit for single-photon avalanche diodes. ICECS (2014)
Fermin Esparza-Alfaro, Salvatore Pennisi, Gaetano Palumbo, Antonio J. López-Martín
Low-Power Class-AB CMOS Voltage Feedback Current Operational Amplifier With Tunable Gain and Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs (8) (2014)
Davide Marano, Giovanni Bonanno, Massimiliano Belluso, Sergio Billotta, Alessandro Grillo, S. Garozzo, Giuseppe Romeo, Alfio Dario Grasso, Salvatore Pennisi, Gaetano Palumbo
A new accurate analytical expression for the SiPM transient response to single photons. ICECS (2014)
Fermin Esparza-Alfaro, Antonio J. López-Martín, Gaetano Palumbo, Salvatore Permisi
CMOS class-AB tunable voltage-feedback current operational amplifier. ICECS (2014)
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi, Giuseppe Di Cataldo
High-performance frequency compensation topology for four-stage OTAs. ICECS (2014)
Elio Consoli, Gaetano Palumbo, Jan M. Rabaey, Massimo Alioto
Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches. IEEE Trans. Very Large Scale Integr. Syst. 22 (7) (2014)
Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro, Alfio Pappalardo
A simple extraction procedure for determining the electrical parameters in Silicon Photomultipliers. ECCTD (2013)
Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
Optimized frequency compensation topology for low-power three-stage OTAs. ECCTD (2013)
Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS. ISSCC (2012)
Gaetano Palumbo, Melita Pennisi, Massimo Alioto
A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2012)
Massimo Alioto, Gaetano Palumbo, Melita Pennisi
A simple keeper topology to reduce delay variations in nanometer domino logic. ISCAS (2012)
Massimo Alioto, Elio Consoli, Gaetano Palumbo
From energy-delay metrics to constraints on the design of digital circuits. Int. J. Circuit Theory Appl. 40 (8) (2012)
Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo
Logic gates dynamic modeling by means of an ultra-compact MOS model. ISCAS (2012)
Elio Consoli, Gaetano Palumbo, Melita Pennisi
Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 20 (2) (2012)
Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo
Behavioral modeling of statistical phenomena of single-photon avalanche diodes. Int. J. Circuit Theory Appl. 40 (7) (2012)
Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale
Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulators. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2012)
Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo
An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2012)
Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo
Verilog-A modeling of SPAD statistical phenomena. ISCAS (2011)
Gaetano Palumbo, Melita Pennisi, Ramón González Carvajal
Figures of merit for class AB input stages. ECCTD (2011)
Massimo Alioto, Elio Consoli, Gaetano Palumbo
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies. IEEE Trans. Very Large Scale Integr. Syst. 19 (5) (2011)
Massimo Alioto, Elio Consoli, Gaetano Palumbo
DET FF topologies: A detailed investigation in the energy-delay-area domain. ISCAS (2011)
Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo
An ultra-compact MOS model in nanometer technologies. ECCTD (2011)
Massimo Alioto, Gaetano Palumbo, Massimo Poli
Optimized design of parallel carry-select adders. Integr. 44 (1) (2011)
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications. ISCAS (2011)
Massimo Alioto, Elio Consoli, Gaetano Palumbo
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit. IEEE Trans. Very Large Scale Integr. Syst. 19 (5) (2011)
Elio Consoli, Gaetano Palumbo, Melita Pennisi
TG Master-Slave FFs: High-speed optimization. ISCAS (2011)
Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo
Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model. ECCTD (2011)
Massimo Alioto, Gaetano Palumbo, Melita Pennisi
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic. IEEE Trans. Very Large Scale Integr. Syst. 18 (5) (2010)
Massimo Alioto, Elio Consoli, Gaetano Palumbo
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
Analytical figure of merit evaluation of RNMC networks for low-power three-stage OTAs. ISCAS (2010)
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
A novel low-power high-speed rail-to-rail class-B buffer amplifier for LCD output drivers. ISCAS (2010)
Davide Marano, Gaetano Palumbo, Salvatore Pennisi
Low-power dual-active class-AB buffer amplifier with self-biasing network for LCD column drivers. ISCAS (2010)

Gaetano Palumbo.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Gaetano Palumbo