A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers.

Gianluca Giustolisi Rosario Mita Gaetano Palumbo Giuseppe Scotti

Published in: IEEE Access (2022)

Keyphrases

low power
power consumption
power reduction
power dissipation
single chip
low power consumption
low cost
logic circuits
high speed
vlsi architecture
gate array
mixed signal
clock gating
real time
digital signal processing
vlsi circuits
cmos technology
design methodology
power management
design considerations