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Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies.
Giuseppe Scotti
Davide Bellizia
Alessandro Trifiletti
Gaetano Palumbo
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2017)
Keyphrases
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high speed
low voltage
low power
cmos technology
design considerations
circuit design
mixed signal
real time
design process
design methodology
power line
computer vision
moving objects
low cost
power dissipation