Davide Bellizia

Publication Activity (10 Years)

Years Active: 2016-2023
Publications (10 Years): 34

Top Topics

Parallel Implementation

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IACR Trans. Cryptogr. Hardw. Embed. Syst.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Ofek Gur, Tomer Gross, Davide Bellizia, François-Xavier Standaert, Itamar Levi
An In-Depth Evaluation of Externally Amplified Coupling (EAC) Attacks - A Concrete Threat for Masked Cryptographic Implementations. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (2) (2023)
Riccardo Della Sala, Davide Bellizia, Giuseppe Scotti
A Novel Ultra-Compact FPGA-Compatible TRNG Architecture Exploiting Latched Ring Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Riccardo Della Sala, Davide Bellizia, Giuseppe Scotti
A Lightweight FPGA Compatible Weak-PUF Primitive Based on XOR Gates. IEEE Trans. Circuits Syst. II Express Briefs 69 (6) (2022)
Riccardo Della Sala, Davide Bellizia, Giuseppe Scotti
High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli Metastable Cells. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Davide Bellizia, Clément Hoffmann, Dina Kamel, Pierrick Méaux, François-Xavier Standaert
When Bad News Become Good News Towards Usable Instances of Learning with Physical Errors. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022 (4) (2022)
Itamar Levi, Davide Bellizia, François-Xavier Standaert
Tight-ES-TRNG: Improved Construction and Robustness Analysis. SN Comput. Sci. 3 (4) (2022)
Dina Kamel, Davide Bellizia, Olivier Bronchain, François-Xavier Standaert
Side-channel analysis of a learning parity with physical noise processor. J. Cryptogr. Eng. 11 (2) (2021)
Davide Bellizia, Balazs Udvarhelyi, François-Xavier Standaert
Towards a Better Understanding of Side-Channel Analysis Measurements Setups. CARDIS (2021)
Davide Bellizia, Nadia El Mrabet, Apostolos P. Fournaris, Simon Pontié, Francesco Regazzoni, François-Xavier Standaert, Élise Tasso, Emanuele Valea
Post-Quantum Cryptography: Challenges and Opportunities for Robust and Secure HW Design. DFT (2021)
Davide Bellizia, Clément Hoffmann, Dina Kamel, Hanlin Liu, Pierrick Méaux, François-Xavier Standaert, Yu Yu
Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021 (3) (2021)
Riccardo Della Sala, Davide Bellizia, Giuseppe Scotti
A Novel Ultra-Compact FPGA PUF: The DD-PUF. Cryptogr. 5 (3) (2021)
Davide Bellizia, Riccardo Della Sala, Giuseppe Scotti
SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks. Cryptogr. 5 (3) (2021)
Itamar Levi, Davide Bellizia, David Bol, François-Xavier Standaert
Ask Less, Get More: Side-Channel Signal Hiding, Revisited. IEEE Trans. Circuits Syst. (12) (2020)
Davide Bellizia, Olivier Bronchain, Gaëtan Cassiers, Vincent Grosso, Chun Guo, Charles Momin, Olivier Pereira, Thomas Peters, François-Xavier Standaert
Mode-Level vs. Implementation-Level Physical Security in Symmetric Cryptography: A Practical Guide Through the Leakage-Resistance Jungle. IACR Cryptol. ePrint Arch. 2020 (2020)
Davide Bellizia, Olivier Bronchain, Gaëtan Cassiers, Vincent Grosso, Chun Guo, Charles Momin, Olivier Pereira, Thomas Peters, François-Xavier Standaert
Mode-Level vs. Implementation-Level Physical Security in Symmetric Cryptography - A Practical Guide Through the Leakage-Resistance Jungle. CRYPTO (1) (2020)
Davide Bellizia, Francesco Berti, Olivier Bronchain, Gaëtan Cassiers, Sébastien Duval, Chun Guo, Gregor Leander, Gaëtan Leurent, Itamar Levi, Charles Momin, Olivier Pereira, Thomas Peters, François-Xavier Standaert, Balazs Udvarhelyi, Friedrich Wiemer
Spook: Sponge-Based Leakage-Resistant Authenticated Encryption with a Masked Tweakable Block Cipher. IACR Trans. Symmetric Cryptol. 2020 (S1) (2020)
Davide Bellizia, Simone Bongiovanni, Mauro Olivieri, Giuseppe Scotti
SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2020)
Itamar Levi, Davide Bellizia, François-Xavier Standaert
Beyond algorithmic noise or how to shuffle parallel implementations? Int. J. Circuit Theory Appl. 48 (5) (2020)
Melissa Azouaoui, Davide Bellizia, Ileana Buhan, Nicolas Debande, Sébastien Duval, Christophe Giraud, Éliane Jaulmes, François Koeune, Elisabeth Oswald, François-Xavier Standaert, Carolyn Whitnall
A Systematic Appraisal of Side Channel Evaluation Strategies. IACR Cryptol. ePrint Arch. 2020 (2020)
Melissa Azouaoui, Davide Bellizia, Ileana Buhan, Nicolas Debande, Sébastien Duval, Christophe Giraud, Éliane Jaulmes, François Koeune, Elisabeth Oswald, François-Xavier Standaert, Carolyn Whitnall
A Systematic Appraisal of Side Channel Evaluation Strategies. SSR (2020)
Itamar Levi, Davide Bellizia, François-Xavier Standaert
Reducing a Masked Implementation's Effective Security Order with Setup Manipulations And an Explanation Based on Externally-Amplified Couplings. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019 (2) (2019)
Davide Bellizia, Giuseppe Scotti, Alessandro Trifiletti
Secure Implementation of TEL-compatible Flip-Flops using a Standard-Cell Approach. ISCAS (2018)
Davide Bellizia, Simone Bongiovanni, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti, Francesco Bruno Trotta
Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks. IEEE Trans. Very Large Scale Integr. Syst. 26 (7) (2018)
Davide Bellizia, Gaetano Palumbo, Giuseppe Scotti, Alessandro Trifiletti
A Novel Very Low Voltage Topology to implement MCML XOR Gates. PRIME (2018)
Dina Kamel, Davide Bellizia, François-Xavier Standaert, Denis Flandre, David Bol
Demonstrating an LPPN Processor. ASHES@CCS (2018)
Davide Bellizia, Giuseppe Scotti, Alessandro Trifiletti
TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2018)
Davide Bellizia, Simone Bongiovanni, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications. IEEE Trans. Emerg. Top. Comput. 5 (3) (2017)
Milena Djukanovic, Davide Bellizia, Giuseppe Scotti, Alessandro Trifiletti
Multivariate Analysis Exploiting Static Power on Nanoscale CMOS Circuits for Cryptographic Applications. AFRICACRYPT (2017)
Davide Bellizia, Danilo Cellucci, Valerio Di Stefano, Giuseppe Scotti, Alessandro Trifiletti
Novel measurements setup for attacks exploiting static power using DC pico-ammeter. ECCTD (2017)
Giuseppe Scotti, Davide Bellizia, Alessandro Trifiletti, Gaetano Palumbo
Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Davide Bellizia, Pietro Monsurrò, Alessandro Trifiletti
VHDL implementation of FWL RLS algorithm. ECCTD (2017)
Davide Bellizia, Milena Djukanovic, Giuseppe Scotti, Alessandro Trifiletti
Template attacks exploiting static power and application to CMOS lightweight crypto-hardware. Int. J. Circuit Theory Appl. 45 (2) (2017)
Davide Bellizia, Giuseppe Scotti, Alessandro Trifiletti
On-chip analog current equalizer as a countermeasure against side-channel attacks in CMOS nanometer technology. MIXDES (2016)
Davide Bellizia, Giuseppe Scotti, Alessandro Trifiletti
Implementation of the PRESENT-80 block cipher and analysis of its vulnerability to Side Channel Attacks Exploiting Static Power. MIXDES (2016)