Analytical figure of merit evaluation of RNMC networks for low-power three-stage OTAs.

Davide Marano Gaetano Palumbo Salvatore Pennisi

Published in: ISCAS (2010)

Keyphrases

low power
figure of merit
power consumption
low cost
high speed
single chip
vlsi circuits
logic circuits
digital signal processing
vlsi architecture
edge detector
cmos technology
low power consumption
mixed signal
gate array
real time
pattern recognition