Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS.
Elio ConsoliMassimo AliotoGaetano PalumboJan M. RabaeyPublished in: ISSCC (2012)
Keyphrases
- power dissipation
- cmos technology
- power consumption
- low power
- nm technology
- energy efficiency
- energy saving
- energy consumption
- silicon on insulator
- high speed
- ultra low power
- metal oxide semiconductor
- product design
- low voltage
- power supply
- vlsi circuits
- analog vlsi
- minimum energy
- low cost
- circuit design
- power management
- low energy
- energy efficient
- life cycle
- random access memory
- bayesian networks
- production planning