A low-power class-AB Gm-C biquad stage in CMOS 40nm technology.
Francesco CenturelliPietro MonsurròAlessandro TrifilettiPublished in: ICECS (2019)
Keyphrases
- low power
- nm technology
- power consumption
- high speed
- low cost
- power dissipation
- single chip
- image sensor
- vlsi circuits
- digital signal processing
- high power
- low power consumption
- vlsi architecture
- logic circuits
- wireless transmission
- mixed signal
- cmos technology
- hardware and software
- power reduction
- pattern recognition
- gate array
- ultra low power