Abdallah Cheikh

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 19

Top Topics

Instruction Set

Computer Architecture

Top Venues

Publications

Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Mauro Olivieri
Exploring Variable Latency Dividers in Vector Hardware Accelerators. PRIME (2024)
Marcello Barbirotta, Francesco Menichelli, Abdallah Cheikh, Antonio Mastrandrea, Marco Angioli, Mauro Olivieri
Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems. IEEE Access 12 (2024)
Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme. IEEE Trans. Computers 73 (7) (2024)
Saeid Jamili, Antonio Mastrandrea, Abdallah Cheikh, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach. ApplePies (2023)
Marcello Barbirotta, Francesco Menichelli, Antonio Mastrandrea, Abdallah Cheikh, Marco Angioli, Saeid Jamili, Mauro Olivieri
Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects. ApplePies (2023)
Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Saeid Jamili, Francesco Menichelli, Mauro Olivieri
Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design. ApplePies (2023)
Saeid Jamili, Abdallah Cheikh, Antonio Mastrandrea, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. ApplePies (2022)
Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration. PRIME (2022)
Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors. IEEE Access 10 (2022)
Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators. ApplePies (2022)
Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. DFT (2021)
Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores. IEEE Micro 41 (2) (2021)
Marcello Barbirotta, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Luigi Blasi, Abdallah Cheikh, Stefano Sordillo, Fabio Di Gennaro, Mauro Olivieri
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment. DFT (2020)
Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores. CoRR (2020)
Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor. ApplePies (2019)
Luigi Blasi, Francesco Vigli, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. ApplePies (2019)
Mauro Olivieri, Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli
Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores. NGCAS (2017)
Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes. CoRR (2017)
Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes. ApplePies (2017)