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Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor.
Abdallah Cheikh
Stefano Sordillo
Antonio Mastrandrea
Francesco Menichelli
Mauro Olivieri
Published in:
ApplePies (2019)
Keyphrases
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design process
highly efficient
design methodology
multithreading
high speed
instruction set
low power consumption
functional verification
high level
np hard
computational power