Antonio Mastrandrea

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 36

Top Topics

Top Venues

Publications

Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Mauro Olivieri
Exploring Variable Latency Dividers in Vector Hardware Accelerators. PRIME (2024)
Gennaro Bellizzi, Alessio Buzzin, Lorenzo Crocco, Antonio Mastrandrea, Noemi Zeni, Sabrina Zumbo, Marta Cavagnaro
A Simple Microwave Imaging System for Food Product Inspection through a Symmetry-Based Microwave Imaging Approach. Sensors 24 (1) (2024)
Marcello Barbirotta, Francesco Menichelli, Abdallah Cheikh, Antonio Mastrandrea, Marco Angioli, Mauro Olivieri
Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems. IEEE Access 12 (2024)
Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme. IEEE Trans. Computers 73 (7) (2024)
Saeid Jamili, Antonio Mastrandrea, Abdallah Cheikh, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach. ApplePies (2023)
Marcello Barbirotta, Francesco Menichelli, Antonio Mastrandrea, Abdallah Cheikh, Marco Angioli, Saeid Jamili, Mauro Olivieri
Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects. ApplePies (2023)
Marco Angioli, Marcello Barbirotta, Antonio Mastrandrea, Saeid Jamili, Mauro Olivieri
Automatic Hardware Accelerators Reconfiguration through LinearUCB Algorithms on a RISC-V Processor. PRIME (2023)
Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Saeid Jamili, Francesco Menichelli, Mauro Olivieri
Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design. ApplePies (2023)
Silvia Casalinuovo, Alessio Buzzin, Antonio Mastrandrea, Ivan Mazzetta, Marcello Barbirotta, Lorenzo Iannascoli, Augusto Nascetti, Giampiero de Cesare, Donatella Puglisi, Domenico Caputo
3D-Printed Face Mask with Integrated Sensors as Protective and Monitoring Tool. AISEM (2022)
Saeid Jamili, Abdallah Cheikh, Antonio Mastrandrea, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. ApplePies (2022)
Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration. PRIME (2022)
Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors. IEEE Access 10 (2022)
Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators. ApplePies (2022)
Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. DFT (2021)
Nicola Bombieri, Silvia Scaffeo, Antonio Mastrandrea, Simone Caligola, Tommaso Carlucci, Franco Fummi, Carlo Laudanna, Gabriela Constantin, Rosalba Giugno
SystemC Implementation of Stochastic Petri Nets for Simulation and Parameterization of Biological Networks. ACM Trans. Embed. Comput. Syst. 20 (4) (2021)
Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores. IEEE Micro 41 (2) (2021)
Alessandro Zompanti, Anna Sabatini, Simone Grasso, Giorgio Pennazza, Antonio Mastrandrea, Giuseppe Ferri, Gianluca Barile, Marco Santonico
A Ladder Network Theoretical Approach for the Automatic Monitoring of Distributed Sensors. AISEM (2021)
Marcello Barbirotta, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Luigi Blasi, Abdallah Cheikh, Stefano Sordillo, Fabio Di Gennaro, Mauro Olivieri
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment. DFT (2020)
Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores. CoRR (2020)
Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor. ApplePies (2019)
Nicola Bombieri, Antonio Mastrandrea, Silvia Scaffeo, Simone Caligola, Franco Fummi, Carlo Laudanna, Gabriela Constantin, Rosalba Giugno
On the Simulation and Automatic Parametrization of Metabolic Networks Through Electronic Design Automation. CIBB (2019)
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
Quality Aware Selective ECC for Approximate DRAM. ApplePies (2019)
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
Full System Emulation of Approximate Memory Platforms with AppropinQuo. J. Low Power Electron. 15 (1) (2019)
Andrea Bartolini, Davide Rossi, Antonio Mastrandrea, Christian Conficoni, Simone Benatti, Andrea Tilli, Luca Benini
A PULP-based Parallel Power Controller for Future Exascale Systems. ICECS (2019)
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
Quality Aware Approximate Memory in RISC-V Linux Kernel. PRIME (2019)
Luigi Blasi, Francesco Vigli, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. ApplePies (2019)
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
Approximate Memory Support for Linux Early Allocators in ARM Architectures. ApplePies (2018)
Giulia Stazi, Federica Silvestri, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing. ApplePies (2018)
Giulia Stazi, Lorenzo Adani, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder. ISC Workshops (2018)
Mauro Olivieri, Usman Khalid, Antonio Mastrandrea, Francesco Menichelli
Characterizing noise pulse effects on the power consumption of idle digital cells. ISCAS (2018)
Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space. NGCAS (2018)
Usman Khalid, Antonio Mastrandrea, Mauro Olivieri
Effect of NBTI/PBTI Aging and Process Variations on Write Failures in MOSFET and FinFET Flip-Flops. CoRR (2017)
Mauro Olivieri, Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli
Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores. NGCAS (2017)
Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes. CoRR (2017)
Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes. ApplePies (2017)
Francesco Menichelli, Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri
An Emulator for Approximate Memory Platforms Based on QEmu. ApplePies (2016)
Usman Khalid, Antonio Mastrandrea, Mauro Olivieri
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops. Microelectron. Reliab. 55 (12) (2015)
Usman Khalid, Antonio Mastrandrea, Mauro Olivieri
Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops. DSD (2014)
Mauro Olivieri, Antonio Mastrandrea
Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Zia Abbas, Antonio Mastrandrea, Mauro Olivieri
A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs. IEEE Trans. Very Large Scale Integr. Syst. 22 (12) (2014)
Mauro Olivieri, Antonio Mastrandrea
A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures. VLSI Design 2013 (2013)