A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer.
Luigi BlasiFrancesco VigliAbdallah CheikhAntonio MastrandreaFrancesco MenichelliMauro OlivieriPublished in: ApplePies (2019)
Keyphrases
- fault tolerant
- hardware architecture
- fault tolerance
- hardware implementation
- low cost
- distributed systems
- instruction set
- real time
- load balancing
- evolvable hardware
- management system
- state machine
- processing units
- design considerations
- protection scheme
- single chip
- high availability
- safety critical
- data acquisition
- low power consumption
- control system
- processing elements
- vlsi implementation
- mobile agents
- fault isolation