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A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design.

Marcello BarbirottaAbdallah CheikhAntonio MastrandreaFrancesco MenichelliFrancesco VigliMauro Olivieri
Published in: DFT (2021)
Keyphrases
  • fault tolerant
  • fault tolerance
  • design methodology
  • distributed systems
  • real time
  • computational power
  • multithreading
  • instruction set
  • state machine
  • high assurance
  • parallel computing
  • fault isolation