Francesco Pappalardo

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 1

Top Topics

Fractional Order

Feedback Control

Simulation Tool

Top Venues

J. Optim. Theory Appl.

Publications

Luca Ezio Pozzoni, Fabrizio Ferrandi, Loris Mendola, Alfio Antonino Palazzo, Francesco Pappalardo
Using High-Level Synthesis to model System Verilog procedural timing controls. DATE (2023)
Riccardo Caponetto, Giovanni Dongola, Francesco Pappalardo, V. Tomasello
Auto-Tuning and Fractional Order Controller Implementation on Hardware in the Loop System. J. Optim. Theory Appl. 156 (1) (2013)
Riccardo Caponetto, Giovanni Dongola, Francesco Pappalardo
Fractional-order simulation tool for the brainstem vestibulo-ocular reflex (VOR). Signal Image Video Process. 6 (3) (2012)
Nathan Ickes, Yildiz Sinangil, Francesco Pappalardo, Elio Guidetti, Anantha P. Chandrakasan
A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip. ESSCIRC (2011)
Mauro Olivieri, Francesco Pappalardo, Simone Smorfa, Giuseppe Visalli
Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units. IEEE Trans. Circuits Syst. II Express Briefs (8) (2007)
Giuseppe Notarangelo, Francesco Pappalardo, Elena Salurso, Elio Guidetti
A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing. J. Low Power Electron. 3 (1) (2007)
Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
Design issues for bus switch systems in deep sub-micro metric CMOS technologies. Circuits, Signals, and Systems (2005)
Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
statistical analysis, for reducing the energy dissipation in a bus-switch encoder. Circuits, Signals, and Systems (2005)
Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
Encoding circuits for low power optical on-chip communications. ISCAS (5) (2005)
Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
Bus-switch coding for reducing power dissipation in off-chip buses. IEEE Trans. Very Large Scale Integr. Syst. 12 (12) (2004)
Francesco Pappalardo, Giuseppe Visalli, Mirko Scarana
An application-oriented analysis of power/precision trade-off in fixed and floating-point arithmetic units for VLSI processors. Circuits, Signals, and Systems (2004)
Giuseppe Notarangelo, Marco Gibilaro, Francesco Pappalardo, Agatino Pennisi, Gaetano Palumbo
Low Power Strategy for a TFT Controller. DSD (2002)
Gaetano Palumbo, Francesco Pappalardo, S. Sannella
Evaluation on power reduction applying gated clock approaches. ISCAS (4) (2002)