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Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design.
Mauro Olivieri
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2002)
Keyphrases
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power dissipation
chip design
power consumption
power reduction
design methodology
low power
vlsi circuits
logic circuits
digital signal processing
cmos technology
high speed
design process
case study
physical design
single chip
circuit design
signal processing
energy efficiency
efficient implementation
nm technology