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An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores.
Mauro Olivieri
Alessandro Trifiletti
Published in:
ISCAS (4) (2001)
Keyphrases
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fine tuned
high speed
fine tuning
circuit design
power consumption
domain specific
dc motor
special purpose hardware
information technology
software components
low power
phase locked loop
real time
digital content
clock frequency
processor core