Renu Mehra

Publication Activity (10 Years)

Years Active: 1995-2015
Publications (10 Years): 0

Top Topics

Top Venues

Publications

Luca Benini, Renu Mehra, Mauro Olivieri
Message from the general chairs. ISLPED (2015)
Renu Mehra
Commercial low-power EDA tools: a review. ISLPED (2012)
Clive Bittlestone, Jim Kardach, Renu Mehra, David Flynn, Barry M. Pangrle
Industry focus session on low-power design. ISLPED (2012)
Luc Séméria, Renu Mehra, Barry M. Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng
RTL c-based methodology for designing and verifying a multi-threaded processor. DAC (2002)
Michael Münch, Norbert Wehn, Bernd Wurth, Renu Mehra, Jim Sproch
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths. DATE (2000)
Renu Mehra, Lisa M. Guerra, Jan M. Rabaey
A partitioning scheme for optimizing interconnect power. IEEE J. Solid State Circuits 32 (3) (1997)
Renu Mehra, Jan M. Rabaey
Exploiting regularity for low-power design. ICCAD (1996)
Renu Mehra, Lisa M. Guerra, Jan M. Rabaey
Low-power architectural synthesis and the impact of exploiting locality. J. VLSI Signal Process. 13 (2-3) (1996)
Paul E. Landman, Renu Mehra, Jan M. Rabaey
An Integrated CAD Environment for Low-Power Design. IEEE Des. Test Comput. 13 (2) (1996)
Jan M. Rabaey, Lisa M. Guerra, Renu Mehra
Design guidance in the power dimension. ICASSP (1995)
Anantha P. Chandrakasan, Miodrag Potkonjak, Renu Mehra, Jan M. Rabaey, Robert W. Brodersen
Optimizing power using transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (1) (1995)