Paul E. Landman

Publication Activity (10 Years)

Years Active: 1995-2015
Publications (10 Years): 1

Top Topics

Learning Algorithm

Top Venues

Publications

Manar El-Chammas, Xiaopeng Li, Shigenobu Kimura, Jesse Coulon, Jake Hu, David Smith, Paul E. Landman, Mark Weaver
15.8 90dB-SFDR 14b 500MS/S BiCMOS switched-current pipelined ADC. ISSCC (2015)
Robert Payne, Paul E. Landman, Bhavesh Bhakta, Sridhar Ramaswamy, Song Wu, John D. Powers, M. Ulvi Erdogan, Ah-Lyan Yee, Richard Gu, Lin Wu, Yiqun Xie, Bharadwaj Parthasarathy, Keith C. Brouse, Wahed Mohammed, Keerthi Heragu, Vikas Gupta, Lisa Dyson, Wai Lee
A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels. IEEE J. Solid State Circuits 40 (12) (2005)
Wai Lee, Paul E. Landman, Brock Barton, Shigeshi Abiko, Hiroshi Takahashi, Hiroyuki Mizuno, Shigetoshi Muramatsu, Kenichi Tashiro, Masahiro Fusumada, Luat Pham, Frederic Boutaud, Emmanuel Ego, Girolamo Gallo, Hiep Tran, Carl Lemonds, Albert Shih, Mahalingam Nandakumar, Robert H. Eklund, Ih-Chin Chen
A 1-V programmable DSP for wireless communications [CMOS]. IEEE J. Solid State Circuits 32 (11) (1997)
Paul E. Landman
High-level power estimation. ISLPED (1996)
Paul E. Landman, Jan M. Rabaey
Activity-sensitive architectural power analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (6) (1996)
Paul E. Landman, Renu Mehra, Jan M. Rabaey
An Integrated CAD Environment for Low-Power Design. IEEE Des. Test Comput. 13 (2) (1996)
Paul E. Landman, Jan M. Rabaey
Activity-sensitive architectural power analysis for the control path. ISLPD (1995)
Paul E. Landman, Jan M. Rabaey
Architectural power analysis: The dual bit type method. IEEE Trans. Very Large Scale Integr. Syst. 3 (2) (1995)