An Integrated CAD Environment for Low-Power Design.

Paul E. Landman Renu Mehra Jan M. Rabaey

Published in: IEEE Des. Test Comput. (1996)

Keyphrases

low power
single chip
low cost
low power consumption
power consumption
vlsi architecture
high speed
logic circuits
computer aided
digital signal processing
design process
real time
power dissipation
computer aided design
gate array
cmos technology
mixed signal
design methodology
high power
efficient implementation