Robert Payne

Publication Activity (10 Years)

Years Active: 1962-2015
Publications (10 Years): 0

Top Venues

VLSIC

CICC

ISSCC

IEEE Trans. Very Large Scale Integr. Syst.

University of Edinburgh, UK (PHD)

Education History

University of Edinburgh, UK

PHD

Publications

Swaminathan Sankaran, Bradley Kramer, Gregory Howard, Benjamin Sutton, Randall Walberg, Vijaylaxmi Khanolkar, Robert Payne, Mark Morgan
An efficient and resilient ultra-high speed galvanic data isolator leveraging broad-band multi resonant tank electro-magnetic coupling. VLSIC (2015)
Manar El-Chammas, Xiaopeng Li, Shigenobu Kimura, Kenneth Maclean, Jake Hu, Mark Weaver, Matthew Gindlesperger, Scott Kaylor, Robert Payne, Charles K. Sestok, William Bright
A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC. IEEE J. Solid State Circuits 49 (9) (2014)
Xiaochen Yang, Robert Payne, Jin Liu
A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCs. CICC (2013)
Yuxiang Zheng, Jin Liu, Robert Payne, Mark Morgan, Hoi Lee
A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-µm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 21 (12) (2013)
Robert Payne, Tatsuya Saito
Session 7 overview: Multi-Gb/s receiver and parallel I/O techniques: Wireline subcommittee. ISSCC (2012)
Robert Payne, Charles K. Sestok, William Bright, Manar El-Chammas, Marco Corsi, David Smith, Noam Tal
A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC. ISSCC (2011)
Jerry Lin, Franz Dielacher, Jing-Hong Conan Zhan, Robert Payne
Good, bad, ugly - 20 years of broadband evolution: What's next? ISSCC (2011)
Robert Payne, Marco Corsi, David Smith, Tien-Ling Hsieh, Scott Kaylor
A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR. IEEE J. Solid State Circuits 45 (12) (2010)
Robert Payne, Marco Corsi, David Smith, Scott Kaylor, Daniel Hsieh
A 16b 100-to-160MS/s SiGe BiCMOS pipelined ADC with 100dBFS SFDR. ISSCC (2010)
Naresh R. Shanbhag, Koichi Yamaguchi, Robert Payne
Energy-efficient high-speed interfaces. ISSCC (2010)
Ali Sheikholeslami, Robert Payne
Will ADCs overtake binary frontends in backplane signaling? ISSCC (2009)
Hao Liu, Jin Liu, Robert Payne, Cy Cantrell, Mark Morgan
A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS. CICC (2009)
Robert Payne
Future of High-Speed Transceivers (Forum). ISSCC (2008)
Robert Payne, Muneo Fukaishi
Multi-GB/s Transceivers. ISSCC (2007)
Robert Payne, Paul E. Landman, Bhavesh Bhakta, Sridhar Ramaswamy, Song Wu, John D. Powers, M. Ulvi Erdogan, Ah-Lyan Yee, Richard Gu, Lin Wu, Yiqun Xie, Bharadwaj Parthasarathy, Keith C. Brouse, Wahed Mohammed, Keerthi Heragu, Vikas Gupta, Lisa Dyson, Wai Lee
A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels. IEEE J. Solid State Circuits 40 (12) (2005)
Richard Goering, Pierre Bricaud, James G. Dougherty, Steve Glaser, Michael Keating, Robert Payne, Davoud Samani
Panel: What is the Proper System on Chip Design Methodology. DAC (1999)
Lawrence Stark, Robert Payne, Yutaka Okabe
Online digital computer measurement of a neurological control system. Commun. ACM 5 (11) (1962)

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Publication Activity (10 Years)

Top Topics

Top Venues

Robert Payne