Lisa M. Guerra

Publication Activity (10 Years)

Years Active: 1992-2000
Publications (10 Years): 0

Publications

Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra
Cut-based functional debugging for programmable systems-on-chip. IEEE Trans. Very Large Scale Integr. Syst. 8 (1) (2000)
Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra
Improving the observability and controllability of datapaths foremulation-based debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (11) (1999)
Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar, Chris Schläger, Bassam Tabbara, Vojin Zivojnovic
Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification. DAC (1999)
Inki Hong, Miodrag Potkonjak, Lisa M. Guerra
Throughput optimization of general non-linear computations. ICCAD (1999)
Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's. IEEE Trans. Very Large Scale Integr. Syst. 6 (1) (1998)
Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
A Methodology for Guided Behavioral-Level Optimization. DAC (1998)
Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra
Functional debugging of systems-on-chip. ICCAD (1998)
Renu Mehra, Lisa M. Guerra, Jan M. Rabaey
A partitioning scheme for optimizing interconnect power. IEEE J. Solid State Circuits 32 (3) (1997)
Miguel R. Corazao, Marwan A. Khalaf, Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
Performance optimization using template mapping for datapath-intensive high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (8) (1996)
Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton
Permissible functions for multioutput components in combinational logic optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (7) (1996)
Renu Mehra, Lisa M. Guerra, Jan M. Rabaey
Low-power architectural synthesis and the impact of exploiting locality. J. VLSI Signal Process. 13 (2-3) (1996)
Jan M. Rabaey, Lisa M. Guerra, Renu Mehra
Design guidance in the power dimension. ICASSP (1995)
Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
Concurrency characteristics in DSP programs. ICASSP (2) (1994)
Miodrag Potkonjak, Lisa M. Guerra, Jan M. Rabaey
Heterogeneous BISR techniques for yield and reliability enhancement using high level synthesis transformations. ASAP (1993)
Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton
Logic Optimization with Multi-Output Gates. ICCD (1993)
Miguel R. Corazao, Marwan A. Khalaf, Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
Instruction set mapping for performance optimization. ICCAD (1993)
Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
High Level Synthesis Techniques for Efficient Built-In-Self Repair. DFT (1993)
Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
High level synthesis for reconfigurable datapath structures. ICCAD (1993)
D. C. Chen, Lisa M. Guerra, E. H. Ng, Miodrag Potkonjak, D. P. Schultz, Jan M. Rabaey
An integrated system for rapid prototyping of high performance algorithm specific data paths. ASAP (1992)