Alessandro Cilardo

Publication Activity (10 Years)

Years Active: 2003-2022
Publications (10 Years): 55

Top Topics

Design Space Exploration

Homomorphic Encryption

Optical Networks

Top Venues

Microprocess. Microsystems

Publications

Vincenzo Maisto, Alessandro Cilardo
A Pluggable Vector Unit for RISC-V Vector Extension. DATE (2022)
Alessandro Cilardo, Marcello Cinque, Luigi De Simone, Nicola Mazzocca
Virtualization Over Multiprocessor Systems-on-Chip: An Enabling Paradigm for the Industrial Internet of Things. Computer 55 (10) (2022)
Alessandro Cilardo, Vincenzo Maisto, Nicola Mazzocca, Franca Rocco di Torrepadula
A Proposal for FPGA-Accelerated Deep Learning Ensembles in MPSoC Platforms Applied to Malware Detection. QUATIC (2022)
Alessandro Cilardo, Stefano Mercogliano
FPGA-based real-time monitoring support for CAN applications. DSD (2021)
Alessandro Biondi, Daniel Casini, Giorgiomaria Cicero, Niccolò Borgioli, Giorgio C. Buttazzo, Gaetano Patti, Luca Leonardi, Lucia Lo Bello, Marco Solieri, Paolo Burgio, Ignacio Sanudo Olmedo, Angelo Ruocco, Luca Palazzi, Marko Bertogna, Alessandro Cilardo, Nicola Mazzocca, Antonino Mazzeo
SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms. IEEE Access 9 (2021)
Alessandro Cilardo
Memory Encryption Support for an FPGA-based RISC-V Implementation. DTIS (2021)
Alessandro Cilardo
Evaluation of HPC Acceleration and Interconnect Technologies for High-Throughput Data Acquisition. Sensors 21 (22) (2021)
Marco Aldinucci, Giovanni Agosta, Antonio Andreini, Claudio Agostino Ardagna, Andrea Bartolini, Alessandro Cilardo, Biagio Cosenza, Marco Danelutto, Roberto Esposito, William Fornaciari, Roberto Giorgi, Davide Lengani, Raffaele Montella, Mauro Olivieri, Sergio Saponara, Daniele Simoni, Massimo Torquati
The Italian research on HPC key technologies across EuroHPC. CF (2021)
Alessandro Cilardo, Marcello Cinque, Luigi De Simone, Nicola Mazzocca
Virtualization over Multiprocessor System-on-Chip: an Enabling Paradigm for Industrial IoT. CoRR (2021)
Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich Cardo, Carles Hernández Luz, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater
The RECIPE Approach to Challenges in Deeply Heterogeneous High Performance Systems. CoRR (2021)
Raffaele Martino, Alessandro Cilardo
SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey. IEEE Access 8 (2020)
Alessandro Cilardo, Mirko Gagliardi, Daniele Passaretti
Hardware support for thread synchronisation in an experimental manycore system. Int. J. Grid Util. Comput. 11 (1) (2020)
Raffaele Martino, Alessandro Cilardo
Designing a SHA-256 processor for blockchain-based IoT applications. Internet Things 11 (2020)
Ramon Canal, Carles Hernández, Rafael Tornero, Alessandro Cilardo, Giuseppe Massari, Federico Reghenzani, William Fornaciari, Marina Zapater, David Atienza, Ariel Oleksiak, Wojciech Piatek, Jaume Abella
Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives. ACM Comput. Surv. 53 (5) (2020)
Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich Cardo, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater
The RECIPE approach to challenges in deeply heterogeneous high performance systems. Microprocess. Microsystems 77 (2020)
Raffaele Martino, Alessandro Cilardo
A Configurable Implementation of the SHA-256 Hash Function. 3PGCIC (2019)
Raffaele Martino, Alessandro Cilardo
A Flexible Framework for Exploring, Evaluating, and Comparing SHA-2 Designs. IEEE Access 7 (2019)
Alessandro Cilardo, Mirko Gagliardi, Vincenzo Scotti
Lightweight hardware support for selective coherence in heterogeneous manycore accelerators. DATE (2019)
Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, Jose Flich, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater
Challenges in Deeply Heterogeneous High Performance Systems. DSD (2019)
Mirko Gagliardi, Edoardo Fusella, Alessandro Cilardo
Improving Deep Learning with a customizable GPU-like FPGA-based accelerator. PRIME (2018)
Davide Zoni, Luca Cremona, Alessandro Cilardo, Mirko Gagliardi, William Fornaciari
PowerTap: All-digital power meter modeling for run-time power monitoring. Microprocess. Microsystems 63 (2018)
Alessandro Cilardo, Nicola Mazzocca, Paolo Prinetto
An abstraction layer enabling pervasive hardware-reconfigurable systems. Int. J. Embed. Syst. 10 (5) (2018)
José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni
Exploring manycore architectures for next-generation HPC systems through the MANGO approach. Microprocess. Microsystems 61 (2018)
Edoardo Fusella, Alessandro Cilardo
Understanding turn models for adaptive routing: The modular approach. DATE (2018)
Edoardo Fusella, Alessandro Cilardo
Reducing Power Consumption of Lasers in Photonic NoCs through Application-Specific Mapping. ACM J. Emerg. Technol. Comput. Syst. 14 (2) (2018)
William Fornaciari, Giovanni Agosta, David Atienza, Carlo Brandolese, Leila Cammoun, Luca Cremona, Alessandro Cilardo, Albert Farres, José Flich, Carles Hernández, Michal Kulchewski, Simone Libutti, José Maria Martínez, Giuseppe Massari, Ariel Oleksiak, Anna Pupykina, Federico Reghenzani, Rafael Tornero, Michele Zanella, Marina Zapater, Davide Zoni
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems. SAMOS (2018)
Domenico Amelino, Mario Barbareschi, Alessandro Cilardo
An IP Core Remote Anonymous Activation Protocol. IEEE Trans. Emerg. Top. Comput. 6 (2) (2018)
Edoardo Fusella, Alessandro Cilardo
Lattice-Based Turn Model for Adaptive Routing. IEEE Trans. Parallel Distributed Syst. 29 (5) (2018)
Alessandro Cilardo
HtComp: bringing reconfigurable hardware to future high-performance applications. Int. J. High Perform. Comput. Netw. 12 (1) (2018)
Edoardo Fusella, Jose Flich, Alessandro Cilardo
Path Setup for Hybrid NoC Architectures Exploiting Flooding and Standby. IEEE Trans. Parallel Distributed Syst. 28 (5) (2017)
Alessandro Cilardo, Mirko Gagliardi, Daniele Passaretti
NoC-Based Thread Synchronization in a Custom Manycore System. 3PGCIC (2017)
Edoardo Fusella, Alessandro Cilardo
ONoC: A Hybrid Optical-Electronic NoC Based on Hybrid Topology. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Jose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Gerald Guillaume, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Simone Libutti, Bruno Maitre, José Maria Martínez, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Tomás Picornell, Igor Piljic, Anna Pupykina, Federico Reghenzani, Isabelle Staub, Rafael Tornero, Marina Zapater, Davide Zoni
MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. DSD (2017)
Domenico Amelino, Mario Barbareschi, Alessandro Cilardo
A Proposal for the Secure Activation and Licensing of FPGA IP Cores. ITASEC (2017)
Rossella Arcucci, Davide Basciano, Alessandro Cilardo, Luisa D'Amore, Filippo Mantovani
Energy Analysis of a 4D Variational Data Assimilation Algorithm and Evaluation on ARM-Based HPC Systems. PPAM (2) (2017)
José Flich, Alessandro Cilardo, Mario Kovaç, Rafael Tornero, Mirko Gagliardi, Edoardo Fusella, José Maria Martínez, Tomás Picornell
Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration. PARCO (2017)
Alessandro Cilardo, Andrea Primativo
Verification of FPGA-augmented trusted computing mechanisms based on Applied Pi Calculus. IACR Cryptol. ePrint Arch. 2017 (2017)
Alessandro Cilardo, Edoardo Fusella
Design automation for application-specific on-chip interconnects: A survey. Integr. 52 (2016)
Edoardo Fusella, Alessandro Cilardo
Crosstalk-Aware Automated Mapping for Optical Networks-on-Chip. ACM Trans. Embed. Comput. Syst. 16 (1) (2016)
Mario Barbareschi, Alessandro Cilardo, Antonino Mazzeo
Partial FPGA bitstream encryption enabling hardware DRM in mobile environments. Conf. Computing Frontiers (2016)
Jose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni
Enabling HPC for QoS-sensitive applications: The MANGO approach. DATE (2016)
Edoardo Fusella, Alessandro Cilardo
PhoNoCMap: An application mapping tool for photonic networks-on-chip. DATE (2016)
Alessandro Cilardo, Mirko Gagliardi, Ciro Donnarumma
A Configurable Shared Scratchpad Memory for GPU-like Processors. 3PGCIC (2016)
Edoardo Fusella, Alessandro Cilardo
Minimizing power loss in optical networks-on-chip through application-specific mapping. Microprocess. Microsystems 43 (2016)
Alessandro Cilardo, Domenico Argenziano
Securing the cloud with reconfigurable computing: An FPGA accelerator for homomorphic encryption. DATE (2016)
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects. ACM Trans. Embed. Comput. Syst. 14 (3) (2015)
Alessandro Cilardo
Variable-latency signed addition on FPGAs. FPL (2015)
Edoardo Fusella, Alessandro Cilardo
Crosstalk-Aware Mapping for Tile-Based Optical Network-on-Chip. HPCC/CSS/ICESS (2015)
Alessandro Cilardo, Jose Flich, Mirko Gagliardi, Rafael Tornero Gavilá
Customizable Heterogeneous Acceleration for Tomorrow's High-Performance Computing. HPCC/CSS/ICESS (2015)
Jose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Alessandro Cilardo, William Fornaciari, Mario Kovac, Fabrice Roudet, Davide Zoni
The MANGO FET-HPC Project: An Overview. CSE (2015)
Edoardo Fusella, Jose Flich, Alessandro Cilardo, Antonino Mazzeo
On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs. SiPhotonics@HiPEAC (2015)
Alessandro Cilardo
New Techniques and Tools for Application-Dependent Testing of FPGA-Based Components. IEEE Trans. Ind. Informatics 11 (1) (2015)
Edoardo Fusella, Alessandro Cilardo, Antonino Mazzeo
Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip. FPL (2015)
Alessandro Cilardo
The HtComp Research Project: An Overview. 3PGCIC (2015)
Alessandro Cilardo, Luca Gallo
Interplay of loop unrolling and multidimensional memory partitioning in HLS. DATE (2015)
Alessandro Cilardo, Luca Gallo
Generating On-Chip Heterogeneous Systems from High-Level Parallel Code. DSD (2014)
Alessandro Cilardo, Davide De Caro, Nicola Petra, Francesco Caserta, Nicola Mazzocca, Ettore Napoli, Antonio Giuseppe Maria Strollo
High Speed Speculative Multipliers Based on Speculative Carry-Save Tree. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2014)
Alessandro Cilardo, Luca Gallo
Improving Multibank Memory Access Parallelism with Lattice-Based Partitioning. ACM Trans. Archit. Code Optim. 11 (4) (2014)
Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides
Area implications of memory partitioning for high-level synthesis on FPGAs. FPL (2014)
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca
Automated design space exploration for FPGA-based heterogeneous interconnects. Des. Autom. Embed. Syst. 18 (3-4) (2014)
Alessandro Cilardo, Dario Socci, Nicola Mazzocca
ASP-based optimized mapping in a simulink-to-MPSoC design flow. J. Syst. Archit. 60 (1) (2014)
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems. DATE (2014)
Alessandro Cilardo, Mario Barbareschi, Antonino Mazzeo
Secure distribution infrastructure for hardware digital contents. IET Comput. Digit. Tech. 8 (6) (2014)
Alessandro Cilardo, Nicola Mazzocca, Luigi Coppolino
TrustedSIM: Towards Unified Mobile Security. UIC/ATC (2013)
Alessandro Cilardo, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca
Efficient and scalable OpenMP-based system-level design. DATE (2013)
Alessandro Cilardo, Nicola Mazzocca
Exploiting Vulnerabilities in Cryptographic Hash Functions Based on Reconfigurable Hardware. IEEE Trans. Inf. Forensics Secur. 8 (5) (2013)
Alessandro Cilardo
Fast Parallel GF(2^m) Polynomial Multiplication for All Degrees. IEEE Trans. Computers 62 (5) (2013)
Alessandro Cilardo, Luca Gallo, Nicola Mazzocca
Design space exploration for high-level synthesis of multi-threaded applications. J. Syst. Archit. 59 (10-D) (2013)
Alessandro Cilardo, Nicola Mazzocca, Paolo Prinetto
Exploring a New Dimension in Code Mobility for Ubiquitous Embedded Systems. UIC/ATC (2013)
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
Automated synthesis of FPGA-based heterogeneous interconnect topologies. FPL (2013)
Alessandro Cilardo
Heterogeneous Computing vs. Big Data: The Case of Cryptanalytical Applications. ICA3PP (2) (2013)
Alessandro Cilardo
The potential of reconfigurable hardware for HPC cryptanalysis of SHA-1. DATE (2011)
Alessandro Cilardo, Carmelo Lofiego, Antonino Mazzeo, Nicola Mazzocca
Revisiting Application-Dependent Test for FPGA Devices. ETS (2011)
Alessandro Cilardo
Exploring the Potential of Threshold Logic for Cryptography-Related Operations. IEEE Trans. Computers 60 (4) (2011)
Alessandro Cilardo, Paolo Durante, Carmelo Lofiego, Antonino Mazzeo
Early Prediction of Hardware Complexity in HLL-to-HDL Translation. FPL (2010)
Alessandro Cilardo, Luigi Esposito, Antonio Veniero, Antonino Mazzeo, Vicenç Beltran, Eduard Ayguadé
A CellBE-based HPC Application for the Analysis of Vulnerabilities in Cryptographic Hash Functions. HPCC (2010)
Alessandro Cilardo
A new speculative addition architecture suitable for two's complement operations. DATE (2009)
Alessandro Cilardo
Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible Pentanomials. IEEE Trans. Computers 58 (7) (2009)
Alessandro Cilardo, Nicola Mazzocca
Time Efficient Dual-Field Unit for Cryptography-Related Processing. VLSI-SoC (Selected Papers) (2008)
Alessandro Cilardo, Nicola Mazzocca, Luigi Coppolino
Virtual Scan Chains for Online Testing of FPGA-based Embedded Systems. DSD (2008)
Alessandro Cilardo, Luigi Coppolino, Antonino Mazzeo, Luigi Romano
Performance Evaluation of Security Services: An Experimental Approach. PDP (2007)
Alessandro Cilardo, Luigi Coppolino, Antonino Mazzeo, Luigi Romano
Combining Programmable Hardware and Web Services Technologies for Delivering High-Performance and Interoperable Security. PDP (2007)
Alessandro Cilardo, Domenico Cotroneo, Cristiano di Flora, Antonino Mazzeo, Luigi Romano, Stefano Russo
Design and implementation of a high performance architecture for providing digital time stamping services to mobile devices. Comput. Syst. Sci. Eng. 22 (3) (2007)
Ferdinando Campanile, Alessandro Cilardo, Luigi Coppolino, Luigi Romano
Adaptable Parsing of Real-Time Data Streams. PDP (2007)
Alessandro Cilardo, Luigi Coppolino, Nicola Mazzocca, Luigi Romano
Elliptic Curve Cryptography Engineering. Proc. IEEE 94 (2) (2006)
Alessandro Cilardo, Antonino Mazzeo, Nicola Mazzocca, Luigi Romano
A Novel Unified Architecture for Public-Key Cryptography. DATE (2005)
Alfredo Benso, Alessandro Cilardo, Nicola Mazzocca, Liviu Miclea, Paolo Prinetto, Szilárd Enyedi
Reconfigurable systems self-healing using mobile hardware agents. ITC (2005)
Alessandro Cilardo, Antonino Mazzeo, Luigi Romano
An FPGA-based Key-Store for Improving the Dependability of Security Services. WORDS (2005)
Alessandro Cilardo, Luigi Coppolino, Antonino Mazzeo, Luigi Romano
High-Performance and Interoperable Security Services for Mobile Environments. HPCC (2005)
Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Giuseppe Cattaneo
A Web Services Based Architecture for Digital Time Stamping. J. Web Eng. 2 (3) (2004)
Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese
Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware. DATE (2004)
Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese
Exploring the design-space for FPGA-based implementation of RSA. Microprocess. Microsystems 28 (4) (2004)
Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Giuseppe Cattaneo
Using Web Services Technology for Inter-enterprise Integration of Digital Time Stamping. OTM Workshops (2003)