Giacinto Paolo Saggese

Publication Activity (10 Years)

Years Active: 2001-2022
Publications (10 Years): 2

Top Topics

Page Segmentation

Native Speakers

Adaptive Filter

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Antonio Giuseppe Maria Strollo, Ettore Napoli, Davide De Caro, Nicola Petra, Giacinto Paolo Saggese, Gennaro Di Meo
Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (6) (2022)
Gennaro Di Meo, Davide De Caro, Giacinto Paolo Saggese, Ettore Napoli, Nicola Petra, Antonio Giuseppe Maria Strollo
A Novel Module-Sign Low-Power Implementation for the DLMS Adaptive Filter With Low Steady-State Error. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
Karthik Pattabiraman, Giacinto Paolo Saggese, Daniel Chen, Zbigniew Kalbarczyk, Ravishankar K. Iyer
Automated Derivation of Application-Specific Error Detectors Using Dynamic Analysis. IEEE Trans. Dependable Secur. Comput. 8 (5) (2011)
Karthik Pattabiraman, Giacinto Paolo Saggese, Daniel Chen, Zbigniew Kalbarczyk, Ravishankar K. Iyer
Dynamic Derivation of Application-Specific Error Detectors and their Implementation in Hardware. EDCC (2006)
Giacinto Paolo Saggese, Anoop Vetteth, Zbigniew Kalbarczyk, Ravishankar K. Iyer
Microprocessor Sensitivity to Failures: Control vs Execution and Combinational vs Sequential Logic. DSN (2005)
Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer
An Experimental Study of Soft Errors in Microprocessors. IEEE Micro 25 (6) (2005)
Nithin Nakka, Giacinto Paolo Saggese, Zbigniew Kalbarczyk, Ravishankar K. Iyer
An Architectural Framework for Detecting Process Hangs/Crashes. EDCC (2005)
Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Giuseppe Cattaneo
A Web Services Based Architecture for Digital Time Stamping. J. Web Eng. 2 (3) (2004)
Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese
Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware. DATE (2004)
Giacinto Paolo Saggese, Claudio Basile, Luigi Romano, Zbigniew Kalbarczyk, Ravishankar K. Iyer
Hardware Support for High Performance, Intrusion- and Fault-Tolerant Systems. SRDS (2004)
Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese
Exploring the design-space for FPGA-based implementation of RSA. Microprocess. Microsystems 28 (4) (2004)
Giacinto Paolo Saggese, Luigi Romano, Nicola Mazzocca, Antonino Mazzeo
A tamper resistant hardware accelerator for RSA cryptographic applications. J. Syst. Archit. 50 (12) (2004)
Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Giuseppe Cattaneo
Using Web Services Technology for Inter-enterprise Integration of Digital Time Stamping. OTM Workshops (2003)
Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Nicola Mazzocca
FPGA-Based Implementation of a Serial RSA Processor. DATE (2003)
Domenico Cotroneo, Cristiano di Flora, Antonino Mazzeo, Luigi Romano, Stefano Russo, Giacinto Paolo Saggese
Providing Digital Time Stamping Services to Mobile Devices. WORDS Fall (2003)
Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo
An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm. FPL (2003)
Beniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. Strollo
A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations. FPL (2002)
Giacinto Paolo Saggese, Antonio G. M. Strollo, Nicola Mazzocca, Davide De Caro
Shuffled serial adder: an area-latency effective serial adder. ICECS (2002)
Antonio G. M. Strollo, Ettore Napoli, Davide De Caro, Giacinto Paolo Saggese
A reconfigurable 2D convolver for real-time SAR imaging. ICECS (2001)
Davide De Caro, Nicola Mazzocca, Ettore Napoli, Giacinto Paolo Saggese, Antonio G. M. Strollo
Test pattern generator for hybrid testing of combinational circuits. ICECS (2001)