Ettore Napoli

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 37

Top Topics

Adaptive Filter

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Ettore Napoli, Antonio G. M. Strollo, Efstratios Zacharelos, Gennaro Di Meo
Comprehensive Analysis of Input Order Invariant Approximate 4-2 Compressors for Binary Multipliers. ISCAS (2024)
Efstratios Zacharelos, Ciro Scognamillo, Ettore Napoli, Diego Gragnaniello
On-Chip Spike Detection and Classification using Neural Networks and Approximate Computing. BioCAS (2023)
Efstratios Zacharelos, Italo Nunziata, Gerardo Saggese, Antonio G. M. Strollo, Ettore Napoli
Approximate squaring circuits exploiting recursive architectures. Integr. 91 (2023)
Gerardo Saggese, Ettore Napoli, Antonio Giuseppe Maria Strollo
CFPM: Run-time Configurable Floating-Point Multiplier. PRIME (2023)
Efstratios Zacharelos, Italo Nunziata, Gerardo Saggese, Antonio G. M. Strollo, Ettore Napoli
Approximate Recursive Multipliers Using Low Power Building Blocks. IEEE Trans. Emerg. Top. Comput. 10 (3) (2022)
Antonio Giuseppe Maria Strollo, Ettore Napoli, Davide De Caro, Nicola Petra, Giacinto Paolo Saggese, Gennaro Di Meo
Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (6) (2022)
Efstratios Zacharelos, Italo Nunziata, Gerardo Saggese, Antonio G. M. Strollo, Ettore Napoli
Approximate Recursive Multipliers Using Low Power Building Blocks. ARITH (2022)
Mauro D'Arco, Ettore Napoli, Efstratios Zacharelos, Leopoldo Angrisani, Antonio Giuseppe Maria Strollo
Enabling Fine Sample Rate Settings in DSOs with Time-Interleaved ADCs. Sensors 22 (1) (2022)
Italo Nunziata, Efstratios Zacharelos, Gerardo Saggese, Antonio Giuseppe Maria Strollo, Ettore Napoli
Approximate Recursive Multipliers Using Carry Truncation and Error Compensation. PRIME (2022)
Gennaro Di Meo, Davide De Caro, Giacinto Paolo Saggese, Ettore Napoli, Nicola Petra, Antonio Giuseppe Maria Strollo
A Novel Module-Sign Low-Power Implementation for the DLMS Adaptive Filter With Low Steady-State Error. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
Ettore Napoli, Efstratios Zacharelos, Mauro D'Arco, Antonio Giuseppe Maria Strollo
Real-Time Downsampling in Digital Storage Oscilloscopes With Multichannel Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (10) (2021)
Gennaro Di Meo, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
Low-power Implementation of LMS Adaptive Filters Using Scalable Rounding. ICECS (2020)
Ettore Napoli, Davide De Caro, Nicola Petra, Antonio G. M. Strollo
A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate. ISCAS (2020)
Mauro D'Arco, Ettore Napoli, Leopoldo Angrisani
A Time Base Option for Arbitrary Selection of Sample Rate in Digital Storage Oscilloscopes. IEEE Trans. Instrum. Meas. 69 (6) (2020)
Mauro D'Arco, Ettore Napoli, Efstratios Zacharelos
Digital Circuit for Seamless Resampling ADC Output Streams. Sensors 20 (6) (2020)
Davide De Caro, Gennaro Di Meo, Ettore Napoli, Nicola Petra, Antonio Giuseppe Maria Strollo
A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization-Free SoC Applications. IEEE Trans. Circuits Syst. (11) (2020)
Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra, Gennaro Di Meo
Low-Power Approximate Multiplier with Error Recovery using a New Approximate 4-2 Compressor. ISCAS (2020)
Antonio Giuseppe Maria Strollo, Ettore Napoli, Davide De Caro, Nicola Petra, Gennaro Di Meo
Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2020)
Ettore Napoli, Davide De Caro, Nicola Petra, Antonio Giuseppe Maria Strollo
A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2020)
Mauro D'Arco, Ettore Napoli, Efstratios Zacharelos
Digital Circuit for the Arbitrary Selection of Sample Rate in Digital Storage Oscilloscopes. ApplePies (2019)
Darjn Esposito, Davide De Caro, Gennaro Di Meo, Ettore Napoli, Antonio G. M. Strollo
Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic. Circuits Syst. Signal Process. 38 (12) (2019)
Gerardo Castellano, Davide De Caro, Darjn Esposito, Paolo Bifulco, Ettore Napoli, Nicola Petra, Emilio Andreozzi, Mario Cesarelli, Antonio G. M. Strollo
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy. Circuits Syst. Signal Process. 38 (7) (2019)
Gennaro Di Meo, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
Variable-Rounded LMS Filter for Low-Power Applications. ApplePies (2019)
Darjn Esposito, Gennaro Di Meo, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
Stall-Aware Fixed-Point Implementation of LMS Filters. PRIME (2018)
Darjn Esposito, Gennaro Di Meo, Davide De Caro, Nicola Petra, Ettore Napoli, Antonio G. M. Strollo
On the Use of Approximate Multipliers in LMS Adaptive Filters. ISCAS (2018)
Darjn Esposito, Gennaro Di Meo, Davide De Caro, Antonio G. M. Strollo, Ettore Napoli
Quality-Scalable Approximate LMS Filter. ICECS (2018)
Darjn Esposito, Antonio Giuseppe Maria Strollo, Ettore Napoli, Davide De Caro, Nicola Petra
Approximate Multipliers Based on New Approximate Compressors. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2018)
Michele De Martino, Davide De Caro, Darjn Esposito, Ettore Napoli, Nicola Petra, Antonio Giuseppe Maria Strollo
A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread- Spectrum Capability. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2018)
Darjn Esposito, Gennaro Di Meo, Davide De Caro, Antonio G. M. Strollo, Ettore Napoli
Design of Low-Power Approximate LMS Filters with Precision-Scalability. ApplePies (2018)
Davide De Caro, Fabio Tessitore, Gianfranco Vai, Gerardo Castellano, Ettore Napoli, Nicola Petra, Claudio Parrella, Antonio G. M. Strollo
Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines. Circuits Syst. Signal Process. 36 (4) (2017)
Ettore Napoli, Gerardo Castellano, Davide De Caro, Darjn Esposito, Nicola Petra, Antonio Giuseppe Maria Strollo
Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2017)
Ettore Napoli, Gerardo Castellano, Davide De Caro, Darjn Esposito, Nicola Petra, Antonio G. M. Strollo
A SISO Register Circuit Tailored for Input Data with Low Transition Probability. IEEE Trans. Computers 66 (1) (2017)
Darjn Esposito, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
On the use of approximate adders in carry-save multiplier-accumulators. ISCAS (2017)
Davide De Caro, Ettore Napoli, Darjn Esposito, Gerardo Castellano, Nicola Petra, Antonio G. M. Strollo
Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2017)
Ettore Napoli, Gerardo Castellano, Darjn Esposito, Antonio G. M. Strollo
Digital circuit for the generation of colored noise exploiting single bit pseudo random sequence. LASCAS (2016)
Darjn Esposito, Gerardo Castellano, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs. ISCAS (2016)
Valerio Marotta, Giuseppe Macera, Michael Peter Kennedy, Ettore Napoli
Comparative analysis of differential colpitts and cross-coupled VCOs in 180 nm Si-Ge HBT technology. ISCAS (2016)
Darjn Esposito, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio Giuseppe Maria Strollo
Variable Latency Speculative Han-Carlson Adder. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2015)
Mariangela Genovese, Paolo Bifulco, Davide De Caro, Ettore Napoli, Nicola Petra, Maria Romano, Mario Cesarelli, Antonio G. M. Strollo
Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images. Integr. 49 (2015)
Giorgio Lopez, Ettore Napoli, Antonio G. M. Strollo
FPGA implementation of the CCSDS-123.0-B-1 lossless Hyperspectral Image compression algorithm prediction stage. LASCAS (2015)
Giorgio Lopez, Ettore Napoli, Domenico Meglio, Antonio G. M. Strollo
An FPGA processor for real-time, fixed-point refinement of CDVS keypoints. ISCAS (2015)
Davide De Caro, Fabio Tessitore, Gianfranco Vai, Nicola Imperato, Nicola Petra, Ettore Napoli, Claudio Parrella, Antonio G. M. Strollo
A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS. IEEE J. Solid State Circuits 50 (9) (2015)
Michael Peter Kennedy, Hongjia Mo, Zhida Li, Guosheng Hu, Paolo Scognamiglio, Ettore Napoli
The noise and spur delusion in fractional-N frequency synthesizer design. ISCAS (2015)
Davide De Caro, Mariangela Genovese, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
Accurate Fixed-Point Logarithmic Converter. IEEE Trans. Circuits Syst. II Express Briefs (7) (2014)
Alessandro Cilardo, Davide De Caro, Nicola Petra, Francesco Caserta, Nicola Mazzocca, Ettore Napoli, Antonio Giuseppe Maria Strollo
High Speed Speculative Multipliers Based on Speculative Carry-Save Tree. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2014)
Mauro D'Arco, Mariangela Genovese, Ettore Napoli, Michele Vadursi
Design and Implementation of a Preprocessing Circuit for Bandpass Signals Acquisition. IEEE Trans. Instrum. Meas. 63 (2) (2014)
Giorgio Lopez, Ettore Napoli, Antonio G. M. Strollo
Towards a Frequency Domain Processor for Real-Time SIFT-based Filtering. ApplePies (2014)
Mariangela Genovese, Ettore Napoli, Davide De Caro, Nicola Petra, Antonio G. M. Strollo
Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA. Integr. 47 (2) (2014)
Mariangela Genovese, Ettore Napoli
ASIC and FPGA Implementation of the Gaussian Mixture Model Algorithm for Real-Time Segmentation of High Definition Video. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Nicola Petra, Davide De Caro, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo
Truncated squarer with minimum mean-square error. Microelectron. J. 45 (6) (2014)
Ettore Napoli, Mauro D'Arco, Pasquale Di Cosmo, Mariangela Genovese, Antonio G. M. Strollo
FPGA based system for the generation of noise with programmable power spectrum. ISCAS (2014)
Mariangela Genovese, Ettore Napoli, Nicola Petra
Hardware performance versus video quality trade-off for Gaussian mixture model based background identification systems. ICDIP (2014)
Giorgio Lopez, Ettore Napoli, Antonio G. M. Strollo
A Frequency Domain Processor for Real-Time CDVS Keypoints Extraction. SITIS (2014)
Davide De Caro, Nicola Petra, Antonio Giuseppe Maria Strollo, Fabio Tessitore, Ettore Napoli
Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2013)
Mariangela Genovese, Ettore Napoli
FPGA-based architecture for real time segmentation and denoising of HD video. J. Real Time Image Process. 8 (4) (2013)
Nicola Petra, Sebastiano Russo, Davide De Caro, Ettore Napoli, Giancarlo Barbarino, Antonio G. M. Strollo
NORA based TDC in 90 nm CMOS. Microelectron. J. 44 (6) (2013)
Francesco Brandonisio, Alberto Prodomo, Michael Peter Kennedy, Ettore Napoli
Implementation of a pulse-holding Time-to-Digital Converter on an FPGA. ECCTD (2013)
Mariangela Genovese, Ettore Napoli, Davide De Caro, Nicola Petra, Antonio G. M. Strollo
FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video. J. Electr. Comput. Eng. 2013 (2013)
Mariangela Genovese, Ettore Napoli
An FPGA-based Real-time Background Identification Circuit for 1080p Video. SITIS (2012)
Michele Riccio, Giuseppe De Falco, Luca Maresca, Giovanni Breglio, Ettore Napoli, Andrea Irace, Yohei Iwahashi, Paolo Spirito
3D electro-thermal simulations of wide area power devices operating in avalanche condition. Microelectron. Reliab. 52 (9-10) (2012)
Mariangela Genovese, Ettore Napoli
FPGA implementation of OpenCV compatible background identification circuit. CompIMAGE (2012)
Valeria Garofalo, Nicola Petra, Ettore Napoli
Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error. IEEE Trans. Computers 60 (9) (2011)
Nicola Petra, Davide De Caro, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo
Design of Fixed-Width Multipliers With Linear Compensation Function. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2011)
Nicola Petra, Davide De Caro, Antonio G. M. Strollo, Valeria Garofalo, Ettore Napoli, Marino Coppola, Pietro Todisco
Fixed-width CSD multipliers with minimum mean square error. ISCAS (2010)
Davide De Caro, Marino Coppola, Nicola Petra, Ettore Napoli, Antonio G. M. Strollo, Valeria Garofalo
High-speed differential resistor ladder for A/D converters. ISCAS (2010)
Nicola Petra, Davide De Caro, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo
Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2010)
Valeria Garofalo, Marino Coppola, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
A novel truncated squarer with linear compensation function. ISCAS (2010)
Valeria Garofalo, Nicola Petra, Davide De Caro, Antonio G. M. Strollo, Ettore Napoli
Low error truncated multipliers for DSP applications. ICECS (2008)
Antonio G. M. Strollo, Davide De Caro, Nicola Petra, Ettore Napoli, Valeria Garofalo
Constrained piecewise polinomial approximation for hardware implementation of elementary functions. ICECS (2008)
Ettore Napoli
Limits and application of the newly proposed deep-depletion SOI LDMOS. IET Circuits Devices Syst. 1 (5) (2007)
Valeria Garofalo, Ettore Napoli, Nicola Petra, Antonio Giuseppe Maria Strollo
Code compression for ARM7 embedded systems. ECCTD (2007)
Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
A high-speed sense-amplifier based flip-flop. ECCTD (2005)
Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra
A novel high-speed sense-amplifier-based flip-flop. IEEE Trans. Very Large Scale Integr. Syst. 13 (11) (2005)
Antonio Giuseppe Maria Strollo, Nicola Petra, Davide De Caro, Ettore Napoli
An area-efficient high-speed Reed-Solomon decoder in 0.25 μm CMOS. ESSCIRC (2004)
Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra
High-speed direct digital frequency synthesizers in 0.25-μm CMOS. CICC (2004)
Davide De Caro, Ettore Napoli, Antonio G. M. Strollo
Direct digital frequency synthesizers with polynomial hyperfolding technique. IEEE Trans. Circuits Syst. II Express Briefs (7) (2004)
Antonio Giuseppe Maria Strollo, Davide De Caro, Ettore Napoli, Nicola Petra
Direct digital frequency synthesis with dual-slope approach. ESSCIRC (2003)
Davide De Caro, Ettore Napoli, Antonio G. M. Strollo
ROM-less direct digital frequency synthesizers exploiting polynomial approximation. ICECS (2002)
Antonio G. M. Strollo, Ettore Napoli, Davide De Caro, Giacinto Paolo Saggese
A reconfigurable 2D convolver for real-time SAR imaging. ICECS (2001)
Antonio G. M. Strollo, Ettore Napoli, Davide De Caro
New design of squarer circuits using Booth encoding and folding techniques. ICECS (2001)
Davide De Caro, Nicola Mazzocca, Ettore Napoli, Giacinto Paolo Saggese, Antonio G. M. Strollo
Test pattern generator for hybrid testing of combinational circuits. ICECS (2001)
Antonio G. M. Strollo, Ettore Napoli, Carlo Cimino
Analysis of power dissipation in double edge-triggered flip-flops. IEEE Trans. Very Large Scale Integr. Syst. 8 (5) (2000)
Antonio G. M. Strollo, Ettore Napoli, Davide De Caro
New clock-gating techniques for low-power flip-flops. ISLPED (2000)
Antonio G. M. Strollo, Ettore Napoli, Carlo Cimino
A VLSI processor for light-weight real-time SAR imaging using signum coded signal and time domain processing. ICECS (1999)
Antonio G. M. Strollo, Carlo Cimino, Ettore Napoli
Power dissipation in one-latch and two-latch double edge triggered flip-flops. ICECS (1999)